A 16-bit ADC produces 2^16 = 65,536 discrete output codes across its full-scale range, while a 24-bit ADC produces 2^24 = 16,777,216 codes, a 256-fold increase in code density [S3]. The smallest theoretically resolvable step, the LSB, shrinks from about 153 microvolts on a 0-10 V, 16-bit channel to roughly 0.6 microvolts on a 0-10 V, 24-bit channel [S6].
The raw code count, however, is a theoretical ceiling. The data sheet headline of a 24-bit ADC such as the Microchip MCP3911 specifies "24-bit resolution with no missing codes," yet the same data sheet lists a typical effective number of bits (ENOB) of about 16, limited by the internal voltage reference, PCB layout, and clock design [S2]. Practically, a data logger spec sheet that quotes only "24-bit ADC" without an ENOB figure is advertising the marketing number, not the metrology number.
Resolution vs ENOB: Two Different Numbers on the Same Chip
Resolution is the count of unique digital codes the converter can output, a fixed function of the bit width, while ENOB captures how many of those codes are actually usable after noise, linearity error, and reference drift are accounted for [S2]. A common engineering rule of thumb on 24-bit sigma-delta ADCs is that real-world ENOB lands in the 16-21 bit range, and on a poorly laid-out PCB it can fall to 12-14 bits even though the data register still reads 24 bits wide [S2][S7].
The implication for instrument selection is direct: a 16-bit ADC specified at 16 ENOB and a 24-bit ADC specified at 16 ENOB will give identical usable precision, so the 16-bit part is the cheaper, lower-power choice. ENOB is also data-rate dependent on sigma-delta parts; halving the output word rate from 1 kSPS to 50 SPS through a sinc^3 filter can recover 1-2 bits of effective resolution by trading bandwidth for averaging [S7].
Compute the LSB You Need Before You Pick the Bit
The DATAQ application note walks through a five-variable worksheet: full-scale data logger input V_D, transducer full-scale output V_S, engineering-unit full scale E, bit count n, and a bipolar/unipolar flag B [S1]. For a ±10 V bipolar (B = 1) input paired with a 5 V full-scale transducer spanning 100 engineering units, a 12-bit ADC resolves 0.098 units; with a unipolar 0-10 V range (B = 0) the same setup resolves 0.049 units [S1]. Crank n from 12 to 16 and the resolution improves 16-fold, from 0.049 to about 0.003 units, which is the working envelope most industrial channels actually need.
Carrying the worksheet one step further, a thermocouple data logger with V_D = ±10 V, V_S = 50 mV, E = 1000 °C, n = 16, and B = 1 yields 0.31 °C per LSB, marginal for profile monitoring but acceptable for trend logging; moving to n = 20 cuts the step to about 0.02 °C, which is the regime where 24-bit parts start to earn their place. For clean 4-20 mA channels from a pressure transmitter the signal-to-noise ratio is high, and a 16-bit ADC is essentially always sufficient, with the bottleneck being the loop's 250 ohm sense resistor tolerance rather than the converter.
When 24-bit Justifies Itself, and When It Does Not
24-bit parts are the right call for sub-millivolt, low-bandwidth sensor chains: load cells at 10-50 SPS, strain-gauge bridges, electrochemical sensors, and weigh scales, where the sigma-delta modulator's oversampling gain delivers genuine ENOB in the 18-21 bit range [S3][S4]. The Adafruit MCP3421 18-bit part at 240 SPS and the Texas Instruments ADS1232 for bridge sensors are typical fits; for a 3-wire resistive soil-moisture probe where the absolute reading is less important than micro-fluctuations, 16-bit at 20 SPS is often enough if the wiring is properly shielded [S4].
24-bit is the wrong call for any of the following: signals above 1 V full scale, sample rates above a few kSPS, cost-sensitive multi-channel systems, and any application where the upstream amplifier or reference cannot outperform the converter's noise floor [S2][S3]. The 4-20 mA output of a flow meter with 0.1 % accuracy is already limited to about 10-bit equivalent absolute accuracy; bolting a 24-bit ADC to that signal spends money on codes the signal cannot use.
Noise Floor and Dynamic Range: The Real Tiebreaker
A 24-bit ADC can in theory reach 144 dB of dynamic range (24 × 6.02 dB), but only a laboratory-grade design with a buried-Zener reference and a 0.1 °C-stabilized front end gets within 20 dB of that figure; production industrial loggers typically achieve 90-110 dB, comparable to a well-designed 16-bit system at 96-98 dB [S3]. A related article on radiometric versus display-ready imaging, 14-bit raw radiometric vs 8-bit AGC video, shows the same principle on a different signal chain: bits beyond the noise floor do not improve the measurement, only the file size.
Dynamic range matters most when the signal of interest is small and rides on a large common-mode or quasi-static offset, for example a 0-50 mV wheatstone-bridge output sitting on a 2.5 V reference. Here the 24-bit part's wider code spread lets the host differentiate microvolt-level bridge deltas without switching gain stages, which simplifies the analog front end at the cost of higher converter noise per code [S3][S6].
Selection Checklist for a New Data Logger
Use the following four-question filter before signing off on a data logger's ADC spec: (1) What is the smallest engineering-unit change the application must resolve, and what is the LSB at the chosen V_D, V_S, E, n, and B [S1]? (2) Is the input a clean 0-5 V or 4-20 mA industrial signal, in which case 16-bit is sufficient, or a sub-100 mV bridge, in which case 24-bit is the right starting point? (3) Does the data sheet quote ENOB, SINAD, or at least noise-free bits at the operating sample rate, or only the headline bit count [S2]? (4) What is the temperature coefficient of the voltage reference, and does it dominate the converter's own drift across the operating window?
For multi-channel systems with shared scan timing, confirm that the converter's per-channel throughput is compatible with the aggregate data rate; an 8-channel 24-bit sigma-delta at 1 kSPS per channel demands 8 kSPS of host-side buffering, which is not free on a low-power PLC front end. For a sealed, battery-powered field logger the 24-bit path typically draws 3-5 mA versus under 1 mA for a 16-bit SAR, so the 24-bit choice is also a power-budget decision. Matching the ADC architecture to the sensor family beats chasing raw bit count, and that is the single biggest cost-versus-performance lever in any data acquisition build [S5][S6].
Trackable signals to watch next: vendor disclosures of ENOB and noise-free bits at 1 kSPS and 50 SPS on new 24-bit sigma-delta parts, and any 2026-2027 product releases that pair 16-bit SAR front ends with on-board 256x oversampling, a path that may close the 16-bit to 24-bit gap without doubling the analog power budget [S6].