U.S. Bureau of Industry and Security (BIS) rules issued October 7, 2022 and tightened October 17, 2023 restrict not only advanced chips but the semiconductor manufacturing equipment (SME) needed to build them, including EUV lithography, advanced etch and advanced deposition tools, with single EUV units priced up to roughly $400 million [S3].
SME accounts for 70-80% of the $10-20 billion cost of a new fab, and global semiconductor sales reached $631 billion in 2024, projected to exceed $1 trillion by 2030, which means any tool restriction ripples into every industrial buyer of logic, memory and analog chips [S3][S4].
What the controls actually block
The current U.S. regime stacks five overlapping restrictions: (1) specific items, EUV lithography and advanced etch/deposition machines need a BIS license; (2) listed end users such as Huawei trigger a license regardless of item; (3) controlled end uses including advanced AI chip production and SME development itself; (4) the Foreign Direct Product Rule (FDPR), which extends U.S. jurisdiction to foreign-built tools made with U.S. technology, software or chips, so a Japanese or Dutch producer shipping into China must clear BIS if any U.S. content is in the tool [S3][S5].
The 2019 Dutch block on EUV shipments to China predates the BIS rule, and Japan plus the Netherlands have since added their own SME export frameworks on top of the multilateral Wassenaar Arrangement, which still includes Russia and so cannot expand unilaterally [S3].
How effective the SME controls have been
In 2026 China is projected to domestically produce only 1-2% of the AI chip volume that U.S. firms produce, a gap the controls created by denying access to the most advanced lithography and deposition steps [S3]. China has matched Western capability only in back-end steps such as packaging and testing, while continuing to depend on stockpiled and older-node imports for the critical front-end layers [S3].
Chinese buyers have worked the seams: Huawei in particular has routed DUV immersion lithography, still legal to ship, through networks of affiliated entities, while enforcement across allied jurisdictions remains uneven [S3]. The result is a leaky but real ceiling on Chinese leading-edge output, not a clean cutoff.
Who the controls are FOR and who they hurt
The controls are FOR U.S. national security buyers who want to slow adversary access to AI training compute, military modernization, and surveillance silicon, the stated rationale under the Export Administration Regulations and EAR classification regime administered by BIS, with defense-trade overlap handled by the State Department Directorate of Defense Trade Controls [S5].
They are NOT for industrial component buyers who simply need MCUs, IGBTs, FPGAs, analog signal-chain parts or mature-node logic. The same regime that blocks EUV shipments to China also forces every tier-2 industrial OEM to re-qualify second sources, extend industrial adhesive and underfill bills of materials for board-level reliability, and absorb longer lead times on commodity parts that share fabs with restricted lines.
Side effects: revenue, R&D and second-source churn
ITIF modelling of a fuller decoupling scenario projects lower revenue for U.S. chipmakers, which reduces R&D spend and weakens long-run competitiveness, a key reason industry groups push back against expansion of the regime [S4]. Real-world data already shows the pressure: Micron exited the China server-chip market after Beijing's 2023 ban on Micron products in critical infrastructure, the kind of tit-for-tat the modelling assumes [S4].
For industrial buyers, the practical translation is a 12-24 month second-source qualification cycle on parts that were previously single-sourced from Chinese fabs, plus tighter warning tape and chain-of-custody requirements on incoming sub-assemblies to document country of origin for EAR audit. The January 2025 proposed AI diffusion rule, which would have capped advanced chip shipments to foreign nations under a three-tier system, was rescinded by the Trump administration, so the current ceiling remains the October 2022 / October 17, 2023 BIS regime plus allied SME rules [S4][S1].
Industrial selection criteria under the new regime
Three criteria now drive industrial chip sourcing: (1) node and country of origin, mature-node logic from non-restricted fabs (28 nm and above) is generally license-free, while sub-14 nm and advanced AI accelerators trigger case-by-case review; (2) U.S. content in the toolchain, since FDPR reaches any foreign tool built with U.S. technology or software, an OEM's compliance posture has to extend to its tooling suppliers, not just the chip vendor; (3) end-use and end-user screening, including deemed-export controls on shared design data with foreign engineers, which forces access control on internal CAD and PDM systems [S3][S5].
Comparison on these three criteria: a 28 nm MCU from a Taiwanese fab (license-free, no FDPR exposure, standard end-use) is the lowest-friction option; a 7 nm SoC from any source is the highest-friction, with license risk tied to both the toolchain and the end application; Chinese-assembled mature-node modules sit in the middle, legal but with heavy documentation overhead.
What the framework still cannot fix
The controls rely on U.S. or allied tool content to extend jurisdiction, so truly indigenous Chinese lithography, if it ever ships, would sit outside FDPR [S3]. Wassenaar's consensus rule and Russia's continued membership cap how aggressive multilateral coordination can get, leaving bilateral alignment with Japan and the Netherlands as the practical lever [S3]. Compliance gaps between U.S. firms and allied firms also persist, and rapid tool evolution means classification lists lag the leading edge by months, not years [S2].
For process engineers, the closing constraint is fab capacity reallocation: AI-grade wafers now absorb leading-node lines, which tightens supply of the mature-node parts that factory automation, motor drives and instrumentation actually run on, visible in multi-quarter backlogs on FPGAs, high-voltage IGBT modules and industrial Ethernet PHYs. Track next: any BIS rule expansion under the post-January 2025 policy direction, and SMIC's reported progress on domestic deep-UV immersion, either would shift the 1-2% Chinese AI output figure that anchors the current risk model [S3][S4].
Industrial buyers watching the second-source queue should also follow the broader allocation story across automation, where chip allocation pushes automation lead times past six months in 2026.