In Q4 2026, flagship AI accelerators span 1,400 W to 2,500 W per board, and the highest-volume rack reference, NVIDIA's GB200 NVL72, is rated up to 132 kW for 72 GPUs, so a single rack envelope now exceeds the entire draw of a mid-2010s hyperscale hall [S2][S4].
The board-power ceiling has jumped roughly 3.6x in five years: the 2020-generation NVIDIA A100 (SXM) sat at 400 W, the 2024 NVIDIA B200 (SXM) hit 1,000 W, AMD's Instinct MI355X now reads 1,400 W, and AMD's MI455X reaches a 2,500 W maximum board power with 23.3 TB/s of HBM4 bandwidth [S2][S4].
Board-power data: the 2026 flagship tier
ScienceShot's checked 10 October 2026 dataset places AMD Instinct MI355X at 1,400 W, the highest single-board reading in the set, with AMD Instinct MI325X and NVIDIA B200 (SXM) tied at 1,000 W, Intel Gaudi 3 (OAM) at 900 W, AMD Instinct MI300X and NVIDIA H100/H200 (SXM) at 700 W to 750 W, and the inference-oriented NVIDIA L4 (PCIe) at 72 W [S2].
AMD's MI455X, ramping in October 2026, pushes the ceiling further: 2,500 W board power, 5.03 PFLOPS dense BF16, 20.13 PFLOPS FP8, 40.27 PFLOPS MXFP4, 432 GB of HBM4, and 23.3 TB/s of memory bandwidth per the AI Compute Tracker review dated 15 October 2026 [S4]. NVIDIA's Rubin GPU, ramping August 2026, is rated 1,800 W on the NVL4 benchmark assumption, with 4 PFLOPS BF16, 17.5 PFLOPS FP8, 35 PFLOPS FP4 training-dense, 288 GB of memory, and 19.2 TB/s of bandwidth [S4].
From board to rack: where the wattage multiplies
Board power is the accelerator's own TDP, but server and rack figures include host CPUs, memory, networking and cooling, so the system-level multiplier is 1.06x to 1.82x above the GPU board number [S2]. NVIDIA DGX H100 is rated 10.2 kW for 8 H100 SXM accelerators (1.27 kW each, 1.82x the 700 W board), DGX B200 is rated 14.3 kW for 8 B200 SXM (1.79 kW each, 1.79x the 1,000 W board), and Intel Gaudi 3 HLB-325 baseboard is rated 7.6 kW for 8 Gaudi 3 OAM at 0.95 kW each, just 1.06x the 900 W board figure [S2].
At rack scale, the GB200 NVL72 reference design is rated up to 132 kW for 72 GPUs, about 1.83 kW per accelerator, and that figure represents facility design capacity rather than a measured draw [S2]. Per-accelerator rack allocation matters more than per-board TDP for grid planning: a single 132 kW rack envelopes the same load as roughly 35 to 40 US households at average residential demand, and 100 of them, a modest cluster, sit at 13.2 MW, well within the scale of a single small gas turbine.
Inference-class silicon pulls the floor down
Not every 2026 accelerator targets the frontier. Intel's Crescent Island D270, formally unveiled 12 October 2026 at the Open Compute Project Global Summit, ships 1.3 PFLOPS of FP8 throughput, 1.5 TB/s of memory bandwidth, 480 GB of on-card LPDDR5X, and 32 Xe3P cores with 256 XMX matrix engines at 350 W under air cooling, an inference-first design built for quantised models where the buyer prizes watts-per-token over peak FLOPs [S3].
Microsoft's Maia 200, live in Azure since January 2026, is rated 5,072 TFLOPS FP8, 10,145 TFLOPS FP4, 216 GB of memory at 7 TB/s, and 750 W board power; the chip serves GPT-5.x-class models at a claimed 30% better performance-per-dollar, and its BF16 figure of 1,268 TFLOPS is a vector-unit rate, not a tensor rate, so it is not directly comparable to GPU dense FP8 [S4]. AWS Trainium3's published per-chip NeuronCore-v4 throughput is 2,517 TFLOPS MXFP8 with 671 TFLOPS dense BF16, sitting in the mid-power inference class [S4].
Criteria comparison: flagship, training-rack, and inference parts
Three decision axes separate the 2026 parts: board power, memory bandwidth, and precision target. The flagship training tier, MI455X at 2,500 W and Rubin GPU at 1,800 W, couples highest HBM bandwidth (23.3 TB/s and 19.2 TB/s respectively) with FP4/FP8 dense rates above 17 PFLOPS, fitting sites where 100+ MW campuses are under construction [S1][S4]. The training-rack tier, MI355X and B200 at 1,000 W to 1,400 W, ships in volume now, and an 8-GPU DGX B200 already draws 14.3 kW, the load of a small commercial building [S2]. The inference tier, D270 at 350 W, Maia 200 at 750 W, Trainium3 in the mid-hundreds of watts, drops power 3x to 7x below the flagship, and trades HBM for LPDDR5X to cut cost-per-inference, the metric that actually drives cloud P&L once training dollars taper.
Power, cooling, and the data-center pipeline
Rack power is now the binding constraint. AMD's Helios reference design, in full production with end-of-Q3 shipments, pairs 72 Instinct MI455X GPUs with 6th Gen EPYC CPUs and Pensando networking over open UALink-over-Ethernet at 2.9 exaflops of FP4 compute; 14 GW of AI compute commitments underpin the platform, with up to 6 GW each from OpenAI and Meta, and up to 2 GW of Helios from Anthropic, announced 23 July 2026 [S1].
A single 132 kW rack needs 3-phase distribution at hundreds of amps; a 100 MW campus is the equivalent of a mid-sized utility substation, and is procured on the same lead-time clock as grid transformers.
What board power does not tell you
Board TDP is a configuration ceiling, not a measured draw. ScienceShot's dataset explicitly excludes host CPU, memory, NICs, and cooling fans, so a real server's wall-plug draw runs 6% to 82% above its GPU board number depending on the platform, and rack-level power is a facility design limit, not a workload measurement [S2].
Many parts are configurable below their maximum, and workload power depends on precision, sparsity utilisation, and memory bandwidth saturation.
What to watch through 2027
Three signals will track the next leg: (1) MI455X and Rubin GPU production-volume shipments, which convert paper TDP into measured facility load, (2) the 14 GW of Helios commitments translating into energised campuses, with OpenAI, Meta, and Anthropic milestones verifiable against earnings and press, and (3) D270, Maia 200, and Trainium3 inference volumes, which determine whether the watts-per-token curve keeps falling or plateaus on LPDDR5X bandwidth limits. [S4]