Bosch runs its full MEMS sensor manufacturing flow at Reutlingen and Dresden, and a single device takes more than three months of fab time across several hundred process steps before it is ready for test [S6]. That single number reframes the entire capacity-planning conversation: MEMS is not a typical CMOS wafer, and a capacity plan built on a "wafers-out per month" spreadsheet will systematically overstate output by ignoring qualification gates and per-die calibration.
The decision an engineering buyer or process planner faces is whether to forecast against finished-die-per-quarter, against wafer-starts, or against revenue-grade qualified units. The answer changes the headcount, the capex curve, and the safety stock by an order of magnitude, because automotive-grade and medical-grade MEMS sensors commonly require 12 to 24 months of validation testing before a production ramp is even authorised [S4].
What "MEMS Capacity" Actually Counts
Capacity is usually quoted as "MEMS sensors shipped per year," but the underlying driver is wafer-starts in a 150 mm or 200 mm line using HARM (High Aspect Ratio Micromachining via deep reactive ion etch on bulk silicon and SOI) plus sacrificial surface micromachining with polysilicon and metal-nitride films [S3]. Throughput on those process modules, not lithography area alone, sets the ceiling. A typical Bosch-class flow of "more than three months" of fab time, on several hundred steps, means WIP sits in the line for a full quarter before any test result lands [S6].
Unit output is therefore decoupled from wafer count: the same 200 mm wafer can yield 5,000 pressure dies or 1,200 multi-axis IMU dies depending on die size and edge-exclusion rules. Plan capacity in die-per-wafer, then in wafer-per-week, then translate to revenue only after the test and calibration funnel is known. The NPL metrology framework treats MEMS as a metrology-limited process, not a photolithography-limited one, and that distinction is what kills naive ramp plans [S3].
Three Capacity Bottlenecks That Override Wafer Count
Bottleneck one: ASIC co-packaging. Integrating a MEMS sensor with its control ASIC adds signal-integrity, thermal-management, and noise-coupling constraints that have to be solved inside the same package, and the assembly yield is dominated by how cleanly the MEMS die talks to the ASIC at the bond-frame level [S2]. Wafer-out numbers mean nothing if a quarter of the dice fail the post-pack trim step.
Bottleneck two: per-die calibration. ST explicitly states that each MEMS sensor requires individual calibration to meet datasheet specifications, because inherent process variability produces slight performance differences between devices from the same wafer [S2]. In practice that means a trim-and-test cell sized to peak wafer-out, not average, plus a fallback for second-pass parts.
Bottleneck three: qualification duration. Automotive and medical programmes lock in 12 to 24 months of validation testing before ramp, which is why MEMS capacity is best modelled as a layered pipeline — wafer-starts feeding a qualification queue feeding a production ramp — rather than a single ramp curve [S4]. Buyers who only watch the ramp curve get blindsided by allocation when one tier in the pipeline stalls.
How the Process Stack Maps to Capacity Sizing
The physical process modules that consume capacity are deposition (vacuum, CVD, epitaxy, silicon dioxide and silicon nitride, spin coating), lithography, etching (wet and dry), laser micromachining, and wafer bonding [S3]. Capacity planners should map each module to a utilisation band: lithography usually runs below 70 percent to leave reticle-change windows, while deep RIE tools and bonders are the first to saturate because of long recipe times and low tool parallelism.
For a gas-sensor variant, an extra constraint appears: metal-oxide semiconductor (MOS) sensing films only react with target gases above a certain temperature, so every micro-hotplate device on a wafer carries an embedded heater that pulls steady-state power, and that heater current must be routed through the same ASIC that handles the sense signal [S1]. Thermal budgeting on the package is part of the capacity plan, not a downstream packaging issue, and it often forces a slower pull-rate per wafer than the lithography module alone would suggest.
On the system side, designers increasingly rely on in-sensor AI to cut data volume and host load — ST's Machine Learning Core (MLC) and Intelligent Sensor Processing Unit (ISPU) architectures embed inference at the edge, but each AI-enabled die still needs the same calibration pass as a raw accelerometer [S2]. The trend lowers the upstream communication burden, not the fab bottleneck.
What the Capacity Plan Is FOR — and What It Is NOT FOR
Capacity planning as described here is FOR OEMs and tier-one integrators with multi-year, multi-platform MEMS buys (automotive safety, industrial IMU, medical pressure, gas-detection modules), where allocation risk in 2024-2026 has been structural rather than cyclical. It is also FOR fab-lite designers who need a defensible second-source strategy, because the long qualification window means swapping suppliers mid-programme is a 12-24 month proposition, not a 90-day PO change [S4].
It is NOT FOR hobby-scale or short-life consumer runs where the qualification tier is lower and the bottleneck is the bill of materials, not the fab. It is also NOT FOR one-off ASIC choices — a wider question of PCB selection inside process control sits upstream of the MEMS decision and is not solved by capacity sizing on its own.
Comparison of the Three Planning Levers
Plan lever 1: wafer-starts per week. Highest volatility, lowest cost-to-change, exposed to reticle and tool downtime. Use it to size the fab capex envelope, not finished-goods supply [S3].
Plan lever 2: qualified-and-released units per quarter. This is the number a buyer actually needs, because it is the only tier that survives the 12-24 month validation gate [S4]. It is also the tier most often misreported, since suppliers tend to quote wafer-out and treat qualification as a sunk cost.
Plan lever 3: calibrated and trimmed units per week. This is the revenue-shippable figure. Per-die trimming is mandatory for ST-class devices because process variability between co-fabricated dice is intrinsic to the technology [S2], so this number is always strictly less than wafer-out, typically by the test-cell yield and the re-trim rework rate.
The most defensible capacity plan builds all three curves on the same time axis, with the lag from lever 1 to lever 2 set by the qualification window and the lag from lever 2 to lever 3 set by the calibration funnel.
Use Cases Where Capacity Planning Bites
Case 1: automotive safety IMU. Long lifecycle, zero-defect expectation, and a 12-24 month validation gate mean a single platform decision locks in 5-7 years of supply from a specific fab [S4]. Plan wafer starts against the platform's peak year, not the launch year.
Case 2: industrial gas detection on MOS micro-hotplate. The sensing film must sit at its operating temperature to react with the target gas, so each device draws continuous heater current and the package thermal budget caps the practical packing density on a wafer [S1]. Plan for the thermal envelope, not the lithography count.
Case 3: consumer-grade pressure and motion sensors. Lower qualification bar, faster ramp, but still subject to the per-die trim step that every ST-class device requires before it ships against its datasheet [S2]. Plan for trim-cell throughput, not wafer-out, when sizing a consumer-line ramp.
Standards, Metrology, and Sourcing Constraints
MEMS production metrology is documented in NPL's framework (NPL Report DEPC-EM 008), which covers profilometry, micro-coordinate measuring machines, electron microscopy, optical microscopy, white-light interferometry, and laser Doppler velocimetry as the core dimensional and dynamic checks supporting a fab [S3]. Buyers specifying a second source should require evidence of this metrology layer, not just ISO 9001 or IATF 16949 certification, because the former proves the fab can see what it is making at micrometer scale.
Process variability between devices on the same wafer is structural to the technology rather than a supplier defect, which is why datasheet-tight MEMS suppliers operate a per-die calibration cell as a standard part of the line, not an option [S2]. Any sourcing decision that assumes "all dice on a wafer are interchangeable" is a planning error with a 100 percent yield penalty.
Closing Signals to Track
Two nodes to watch over the next planning cycle: (1) Bosch-class process-flow duration, currently quoted at "more than three months" across several hundred steps from a manufacturer with two dedicated 200 mm sites in Germany [S6] — any published drop below that figure would be a real capacity-curve event, and (2) the qualification-window range of 12-24 months for automotive and medical grades [S4], where a regulatory move toward shorter validation (e.g. AEC-Q100 reinterpretation or IEC 60601 update) would compress the pipeline lag. Cross-check both against the per-die calibration obligation that every datasheet-grade MEMS device must clear before it ships [S2].
The underlying component specifications are covered under capacitive sensor, displacement sensor, and flow sensor.