Analog and power management ICs are quoted at 26-40 weeks across 2026, with the trend labelled Worsening as AI power demand absorbs mature-node fab output [S1].
On July 3, 2026 Analog Devices told customers that lead times on a portion of its portfolio are extending up to six months, and asked buyers to place orders at least six months in advance through their preferred channel partner [S2][S3].
Category-level lead-time snapshot, first half 2026
Power semiconductors and analog ICs sit in the 26-40 week bracket, behind MCUs (30-55+ weeks) and FPGAs (40-52 weeks) but ahead of MLCCs and passives at 12-26 weeks [S1]. RF components run 30-40+ weeks and stay Tight, while standard logic and discretes at 10-20 weeks are Near normal [S1]. Within the automotive slice, average semiconductor lead times rose to 16.8 weeks in Q1 2026, with substantial increases concentrated in interface ICs, power management ICs, and adjacent categories [S7].
The Susquehanna Financial Group Lead Time Index (LTI) printed approximately 26 weeks as a weighted average across MCU, analog, power discrete, FPGA and standard logic categories in Q1 2026, still well above the 17-19 week pre-pandemic baseline and 7+ weeks short of the 27.1-week mid-2022 peak [S4]. Industry billings ran about 18% year on year through Q1 2026 per SIA data referenced in the same report [S4].
What ADI actually said, and what it means for signal-chain buyers
ADI's July 3, 2026 customer notice cites broad-based demand growth and asks buyers to extend backlog coverage and order through their preferred channel partner at least six months ahead; the letter does not list which product families are impacted [S2]. Industry coverage points to signal-chain, data-converter, industrial automation, automotive, communications, test and measurement, and power management as the categories where ADI devices are deeply embedded and substitution carries the longest re-qualification cost [S2][S3].
Pricing pressure had already shown up earlier in 2026, with ADI adjusting selected product categories and customer segments at varying rates, the larger increases landing on higher-end devices and longer lead-time parts [S3]. For buyers, the practical effect is that cost and delivery risk are now moving together: pricing has firmed, and order-to-dock windows have widened, with a 6-month lead time on impact-portfolio parts becoming the planning floor rather than the ceiling [S2][S3].
Three lead-time numbers, one planning reality
Quoted lead time is the number the manufacturer publishes on its order acknowledgement; committed lead time is the contractual date a distributor writes on the PO (usually with a push-out clause); actual lead time is calendar time from PO entry to dock receipt, and is the only number that drives production planning [S4]. Across MCU, analog and power-discrete lines the gap between quoted and actual averages 4-10 weeks in Q1 2026, driven by allocation re-balancing and uneven foundry utilisation [S4].
Texas Instruments MCU portfolio illustrates the spread: 8-14 weeks quoted versus 16-22 weeks actual per distributor channel commentary in early 2026, and the same pattern of quoted-vs-actual divergence shows up across Arrow, Avnet and WPG earnings call commentary on push-out rates for allocated automotive lines [S4]. Independent distributor stock typically compresses the bridge to 3-10 business days when a part is sourceable on the secondary market with full anti-counterfeit traceability, useful as a tactical hedge but not a substitute for forward coverage [S1][S4].
Why 2026 is different: AI demand, mature nodes, and tool lead times
Three forces are stacking. AI data-centre build-outs are absorbing power management ICs, voltage regulators and high-bandwidth memory, pushing average utilisation at the top 10 foundries to roughly 90 percent on mature 8-inch nodes, the same nodes that make the everyday parts in automotive, industrial and medical products [S1]. Memory makers have shifted capacity toward AI-grade parts, and DRAM and NAND price spikes of 40-70% are forecast through mid-2026 [S1].
Capacity cannot respond quickly because ASML EUV scanner lead time is 18-24 months per the ASML Q1 2026 earnings call commentary, and broader semiconductor manufacturing tool lead times run 18-24 months industry-wide, so material relief on constrained lines is unlikely before late 2027 [S1][S4]. A related dynamic flagged in power-semiconductor sourcing is the SiC Paradox, where high-end SiC demand is colliding with industrial traction and EV inverter build-outs; estimated lead times for high-end power components are 20-30+ weeks [S6]. The cross-category consequence is that power ICs, memory and MCUs move together in 2026 because they share fab capacity with AI demand, so a slip on one BOM line tends to foreshadow the others [S1]. For context on how this pull is reshaping the broader market, see this analog chip market 2026 industrial and automotive pull assessment.
Comparison: lead-time, push-out risk and substitution cost by sub-category
The table below lines up the main sub-categories on three decision criteria a sourcing engineer actually uses: quoted lead time, quoted-vs-actual push-out risk, and re-qualification cost if a second source is used. Numbers and risk tags are drawn from the research [S1][S4][S6][S7].
Automotive PMICs and interface ICs: 16.8 weeks average automotive lead time in Q1 2026 [S7], high push-out risk reported by Arrow, Avnet, WPG on allocated automotive lines [S4], high re-qualification cost because AEC-Q100 and OEM-specific PPAP gates apply. High-end power discrete (including SiC): 20-30+ weeks [S6], medium push-out risk as foundry allocation re-balances, medium-to-high re-qualification cost driven by inverter and converter re-validation. General-purpose analog ICs (ADI impact portfolio): up to 26 weeks (6 months) on the named portion of ADI's portfolio [S2][S3], medium push-out risk, high re-qualification cost because precision signal-chain and data-converter swaps trigger board-level re-characterisation. MCUs: 30-55+ weeks [S1], high push-out risk, high re-qualification cost given firmware lock-in and toolchain differences. Standard logic and discretes: 10-20 weeks, near normal [S1], low push-out risk, low re-qualification cost as second sources are usually drop-in.
What procurement teams can do, in 2026 terms
Extend the planning horizon past the longest quote: if a critical MCU is 55 weeks, a 12-month forecast is already too short, and leading OEMs are placing non-cancellable orders 18-24 months out on constrained lines [S1]. Qualify second sources before you need them, because a pin-compatible alternate that is qualified today converts a 55-week problem into a purchasing decision rather than a redesign [S1].
Audit the BOM lines that fail together, not the one that slipped first: power ICs, memory and MCUs share mature-node capacity in 2026, so a single slip usually has companions [S1]. Use verified independent stock as a bridge, with full anti-counterfeit inspection, for the 3-10 business day window that authorised quotes cannot match [S1][S4]. And lock alternates for end-of-life parts immediately, because last-time-buy windows are shrinking while demand for remaining stock rises [S1]. For the broader magnet and lamination angle on the power side, this amorphous core transformer GOES workaround spec reality check is a useful parallel read.
Trackable signals to watch next
Two nodes are worth monitoring into Q4 2026: the next monthly Susquehanna LTI release for any further drift in the ~26-week industry average, and the next ADI customer letter or earnings call for whether the six-month lead-time notice is broadened, narrowed, or rolled back [S2][S4]. Foundry utilisation on mature 8-inch nodes staying near 90% would confirm the Worsening tag on power and analog through year-end, while any softening toward 80% would suggest allocation is starting to ease before the EUV tool bottleneck relaxes in late 2027 [S1][S4].
Detailed specification references: energy management, lead screw, and time relay.