GAA transistor revenue reached USD 764.04 million in 2026, up from USD 677.10 million in 2025, and is projected to grow to USD 2,008.25 million by 2034 at a 12.84% CAGR [S2].
TSMC continued volume ramp of its N2 (2-nanometer) nanosheet GAA process across Hsinchu and Kaohsiung fabs through 2025, targeting smartphone and high-performance computing customers [S1].
GAA architecture vs FinFET: the physical driver
Planar MOSFETs hit a wall near 22 nm, where the flat gate lost electrostatic control and short-channel leakage surged; FinFETs extended scaling by wrapping the gate on three sides of a vertical fin from 16 nm downward, but at 3 nm and below FinFET variability starts to explode and a fourth-side wrap is required [S3][S4]. In a GAA device the gate surrounds the channel on all four sides, typically implemented as stacked horizontal nanosheets of alternating silicon and silicon-germanium, which improves drive current, lowers leakage, and gives better subthreshold swing at sub-3 nm nodes [S3][S5].
The engineering tradeoff is real: stacking nanosheets boosts effective channel width per footprint, but defect-free wrap of very thin silicon or III-V channels and uniform gate formation are open manufacturing challenges [S5]. Nanosheet GAA already took 55% of the 2024 device-type market, with nanowire GAA the second-largest architecture at roughly 30% [S1][S2].
Market sizing: USD 764 million in 2026, doubling by 2034
SNS Insider values the 2025 GAA market at USD 685 million rising to USD 2,283 million by 2035 (12.8% CAGR); Precedence Research values 2025 at USD 677.10 million, 2026 at USD 764.04 million, and 2034 at USD 2,008.25 million (12.84% CAGR) [S1][S2]. The two sources diverge on 2035 endpoint but agree on the 12.8-12.84% CAGR band, which is the figure engineers should anchor to when sizing capacity. The United States alone is modeled at USD 108 million in 2025 growing to USD 476 million by 2035 (16.0% CAGR) on CHIPS Act incentives and hyperscaler AI accelerator demand [S1].
Asia Pacific held 60% of 2024 revenue and remains the production center; North America is the fastest-growing region at a 25% projected CAGR through 2034 [S2]. Foundries captured 50% of 2024 end-user share, with IDMs also among the tracked end-user segments over 2026-2035 [S1][S2].
Node mix: 5nm/4nm at 45%, 3nm/2nm at 40% in 2024
5nm/4nm nodes held the largest 2024 share at 45% of revenue, with 3nm/2nm nodes at 40% but growing at a significant forward CAGR, reflecting that GAA is simultaneously ramping at the previous-generation production node and seeding the next [S2]. Synopsys confirms GAA emerged at 3nm and is dominant at 2nm, with high-performance mobile leading adoption and hyperscale servers plus high-performance CPUs following [S3].
By application, high-performance computing carried 35% of 2024 share; mobile SoCs are the fastest-growing application at 25% CAGR through 2034 [S2]. Automotive EV chipsets and 5G infrastructure are listed as emerging demand drivers, though no node-level share is given for those segments in the research [S1].
Foundry and IDM ramps: TSMC N2, Intel 18A, Samsung 2nm
TSMC is in volume ramp on N2 nanosheet GAA through 2025 at Hsinchu and Kaohsiung; Intel Foundry advanced qualification of its RibbonFET GAA architecture through 2025 on 20A and 18A process nodes, securing early customer engagements for next-generation logic at its U.S. fabs [S1]. Samsung's MBCFET (multi-bridge channel FET) is the third publicly named GAA implementation but is not detailed in the supplied research, so its node status is left as unverified. The research does not break out wafer-start volumes per foundry, only aggregate market revenue and node-level mix.
For process engineers this means design kits for nanosheet GAA at 3nm and 2nm are the most mature, and the ecosystem expectation, per Synopsys, is that GAA, combined with new power distribution schemes and multi-die packaging, will carry scaling into the angstrom era [S3].
Comparison: nanosheet vs nanowire GAA vs forksheet
Three GAA sub-architectures are tracked in the research. Nanosheet GAA (stacked horizontal Si/SiGe sheets) dominated with 55% 2024 share and is the volume-production choice at TSMC N2 and Intel 18A [S2]. Nanowire GAA (cylindrical Si or III-V wires, smaller cross-section) held about 30% 2024 share and is the highest-growth sub-architecture through 2034 [S2]. Forksheet (a 2026-2035 trend item) is described as the next step beyond nanosheet toward sub-2 nm, with the gate reaching into the n-p separation region for tighter n-to-p spacing, but no commercial foundry node is confirmed in the research [S1].
Selection rule of thumb: nanosheet for high drive current per footprint at 3nm/2nm production today, nanowire for ultimate electrostatic control in research and select IDM programs, forksheet as the roadmap option once nanosheet density gains flatten. The research does not assign specific current density (uA/um) figures per architecture, so any quantitative claim there is unsupported.
Limitations, open questions, and what to track next
Yield and defect density at sub-2 nm are not disclosed in the research, which is a real gap for anyone trying to forecast wafer pricing or die cost. The 12.84% CAGR is a revenue figure, not a unit or wafer-start figure, so it can move with mix shift toward higher-ASP AI accelerator dies rather than pure volume growth [S2]. Whether forksheet reaches production before 2028 is implied as a trend but not dated [S1].
Trackable signals worth watching: TSMC N2 volume-ramp disclosures and 2nm-capex updates through 2026, Intel 18A RibbonFET customer wins and high-volume manufacturing timing, Samsung 2nm GAA production readiness, and any revision to the 3nm/2nm share figures as 2025 wafer-start data lands. The U.S. CHIPS-funded fab build-out is cited as a regional growth driver in the source research [S1].
For a related deep dive on the broader FinFET-to-GAA transition, see the encyclopedia entry on the gate-all-around transistor architecture.