TSMC lifted prices 5-10% on N5, N4, and N3 wafers in 2026, while Samsung pushed 4nm, 5nm, and 8nm quotes up by 10-15% on new orders placed from July [S2][S8]. 2nm wafers are tracking near $30,000 per wafer, a roughly 50% premium over 3nm's ~$20,000 baseline [S1][S2].
TSMC's 3nm line is fully booked through 2027, with six anchor customers (Apple, Nvidia, AMD, Broadcom, Qualcomm, MediaTek) exploring Samsung and Intel as second sources [S1]. 8-inch mature-node utilization is forecast to climb from 75-80% in 2025 to 85-90% in 2026, dragging power management IC, display driver, and industrial MCU wafer prices up with it [S1][S5].
TSMC Advanced-Node Pricing: Sub-5nm Up 5-10%, 2nm Near $30,000
TSMC's 2026 increase targets N5, N4, and N3 with per-customer variation by volume, framed as a structural response to tariffs, capex pressure, and currency shifts [S2]. Wafer costs at 2nm reach approximately $30,000 against a 3nm baseline of ~$20,000, a 50% step that breaks the historical "shrink saves cost per transistor" rule for the first time in a major node transition [S1]. The company's 53% gross-margin floor and 2026 capex of $52-56 billion make higher wafer prices an arithmetic necessity, not a discretionary move [S1].
Capacity is the lever. TSMC's 3nm line is fully booked through 2027, with order visibility extending across the advanced-node stack [S1][S5]. The pricing push cascades downstream: OSAT providers running near 90% utilization pass costs through, analog suppliers facing tighter wafer allocations raise quotes, and mature-node fabs serving AI-server power management join the repricing wave [S1].
Samsung Foundry: SF4 Up 10-15%, Demand Spike Forces Quotation Reset
Samsung raised new-order prices on its 4nm SF4 process by 10-15% in July 2026, with similar 4nm, 5nm, and 8nm increases reported through August [S6][S8]. The driver is demand filling its 4nm lines after a major order inflow, with Samsung explicitly preparing additional increases rather than absorbing utilization gains as margin [S6].
That dynamic reframes Samsung as a credible second source rather than a discount alternative. With TSMC's sub-5nm capacity locked, hyperscalers and chip designers needing volume hedge are now accepting Samsung's higher list prices, a structural change from the historical pattern where Samsung undercut TSMC on leading-edge [S1][S6]. For procurement teams running dual-foundry risk models, the second-source premium has narrowed substantially.
Mature Nodes: 8-Inch Tightens to 85-90% Utilization, 12-Inch Mature Stays Soft
TrendForce projects global 8-inch wafer foundry utilization at 85-90% in 2026, up from 75-80% in 2025, driven by power management IC demand from AI servers, EVs, and edge devices [S1][S5]. The shift is amplified by strategic capacity cuts at major foundries, removing historical buffer that kept 8-inch pricing stable through previous cycles [S5].
12-inch mature nodes (28nm and above) tell the opposite story. Soft consumer electronics, combined with rising memory costs squeezing end-device BOMs, keeps 12-inch mature growth momentum suppressed [S5]. The split creates a polarized landscape: advanced and 8-inch tight, 12-inch mature slack, a pattern that complicates wafer sourcing for mixed-node products. For industrial buyers, this means pressure transmitter and flow meter designs that depend on mixed 28nm/12nm+ MCU plus 8-inch analog die will see non-uniform cost pressure across the bill of materials.
Comparison: Foundry Pricing Moves by Vendor and Node (2026)
Reading the four major repricing vectors side by side clarifies where BOM impact lands: [S1]
TSMC sub-5nm (N5/N4/N3): +5-10% in 2026, 3nm booked through 2027, 53% gross-margin floor anchor [S1][S2]. TSMC N2: ~$30,000 per wafer, ~50% premium over 3nm's $20,000, entering HVM H2 2025 [S1][S2]. Samsung SF4 (4nm): +10-15% on July new orders, 5nm/8nm following similar trajectory [S6][S8]. VIS and other mature 8-inch foundries: utilization up to 85-90%, selective price increases, BCD and power lines specifically affected [S1][S4][S5].
The decision criterion is simple: if your design lives on N3 or below, expect a 5-10% wafer cost increase and queue pressure through 2027. If you run on 8-inch analog or BCD, expect mid-single-digit to low-double-digit increases as utilization tightens. If you sit on 12-inch mature, your wafer cost trajectory remains the soft spot in the bill of materials [S4][S5].
Cost Drivers and Total-Cost-of-Ownership Shift
Four cost drivers define the 2026 foundry repricing. Capex intensity: TSMC's $52-56 billion 2026 program plus CoWoS packaging expansion flow directly into per-waer amortization at the leading edge [S1][S5]. Demand concentration: AI accelerator orders from CSPs and AI startups lock advanced capacity, removing the negotiation buffer that historically capped annual increases at low single digits [S1][S5]. Currency and tariff exposure: TSMC explicitly cited tariffs, CAPEX, currency fluctuations, and supply-chain pressure as triggers for the 5-10% move [S2]. Mature-node demand spillover: power management IC and display driver demand from AI servers and EVs pulled 8-inch utilization from 75-80% to 85-90% in a single year [S1][S5].
Total-cost-of-ownership math shifts because the repricing is not uniform across nodes. A mixed-node product carrying a 28nm MCU, an 8-inch analog front-end, and a leading-edge AI accelerator sees three different cost trajectories in one BOM. Engineers respond by redesigning for second-source availability, node flexibility, packaging and test simplification, and longer product lifetimes to avoid requalification churn, a shift from "design-to-cost" to "design-to-supply" [S4]. For buyers, the procurement decision now weighs pressure sensor and industrial valve lifecycles against requalification cost on semiconductors that may see two wafer-price resets before the next hardware revision.
Strategic Consequences: Second-Source Sourcing and BOM Risk Scoring
The repricing wave makes single-foundry designs structurally weaker. With TSMC's advanced capacity locked and Samsung's prices now tracking within 10-15% of TSMC's own increases, the historical rationale for sole-sourcing on cost has eroded [S1][S6][S8]. A foundry sourcing strategy that pairs TSMC N3 with Samsung SF4, or TSMC N5 with a VIS or UMC mature-node partner, spreads exposure across vendors whose price cycles now diverge meaningfully.
BOM risk scoring by lifecycle stage and source count becomes a primary design input rather than a procurement afterthought, especially for industrial products with 10-15 year field lives [S4]. Two trackable signals to watch: whether TSMC's reported 3-6% January 2027 increase holds at the lower end given visible 3nm capacity tightness, and whether Samsung's 10-15% July 2026 quote push sustains into 2027 as second-source orders convert from quotes to volume [S3][S8].
Closing: The 2026 foundry repricing is broad, structural, and confirmed across at least four independent reports spanning February through September [S1][S4][S5][S7]. Next node: monitor the reported TSMC 3-6% January 2027 list adjustment and any follow-on Samsung 2nm quotations, both of which will set the baseline for advanced-node cost models into 2027 [S3].
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