Samsung demonstrated a 900-layer 3D NAND die on 28 May 2026 by string-stacking two 450-layer arrays, a near 3x jump over the 321-layer devices shipping from SK hynix today [S2].
The mainstream NAND supplier field now spans Solidigm at 192 layers, SK hynix at 321 layers, and Samsung moving from 286-layer 9th generation V-NAND in 2024 toward 400-layer 10th generation mass production in 2026 [S2][S4]. A 1,000-layer chip is targeted by Samsung for 2030, with the 11th generation V-NAND planned for 2027 alongside an estimated 50% I/O rate improvement [S4].
Where the layer count stands on 2026-09-20
SK hynix's 321-layer device and Solidigm's 192-layer part bracket the current shipping range, while Samsung's 10th generation 400-layer V-NAND is in mass-production transition during 2026 [S2][S4]. Layer count above 200 is now the commercial baseline across at least three suppliers [S5].
PatSnap's April 2026 landscape report documents wordline layer counts progressing from 24 layers at inception to 176+ layers in 2021, with the 200+ layer threshold now exceeded by every leading vendor [S5]. Channel hole aspect ratio and wordline RC delay, not raw cell count, are the binding constraints above 300 layers [S1].
String-stacking versus monolithic HAR etch
Samsung's 900-layer device is built by bonding two 450-layer strings together rather than etching a single 900-layer channel hole, sidestepping the high-aspect-ratio etch ceiling that limits monolithic stacks [S1][S2].
String-stacking is increasingly the consensus path beyond 500 layers because a single 1,000-layer channel hole would push HAR etch beyond the economic limit of conventional fluorine-based chemistries, per Lam Research and ACM Research commentary [S1]. SK hynix already applies a two-tile string-stacking approach at 321 layers, which is why a 1,000-layer monolithic target is treated as a stretch goal across the industry [S1][S2].
Hybrid bonding introduces a new failure mode: wafer warpage from the thicker combined stack, which Samsung addressed with an Upper Chuck flatness fixture and overlay correction technology on the 900-layer research die [S2].
Three concurrent scaling axes beyond layer count
Layer count is one of three scaling levers; logical bits per cell and CMOS-under-array (CuA) integration are the other two, and PatSnap's 2026 analysis treats them as a coupled system rather than independent choices [S5].
Logical scaling has progressed from SLC (1 bit) through MLC (2), TLC (3), QLC (4), to experimental PLC at 5 bits, with 31 charge states plus empty demanding heavier error correction [S1][S5]. CMOS-under-array, also called Cell-on-Peri, relocates peripheral circuits under the memory array to shrink die footprint; Samsung's 10th generation claims a 1.6x bit-density gain over the prior node using a Bonding Vertical NAND architecture that separates storage and peripheral wafers before bonding [S4][S5].
For comparison on the three scaling axes, the table below lines up the main options in 2026:
What the 300-layer threshold actually changed
Stacking beyond 300 layers exposed mechanical damage in the cell stack during Samsung's 9th generation development, forcing the shift to Bonding Vertical NAND and a peripheral/storage split [S4].
Channel hole aspect ratio above 80:1 begins to transition the etched profile from a macaroni shape to a nanowire cross-section, producing a ΔVth gradient between top and bottom cells that has to be corrected with non-uniform Gaussian channel doping [S5]. Read current drops as the total polysilicon channel resistance scales with layer count, so Samsung also revised bitline and wordline structures on the 900-layer research die to hold die size and power in check [S2].
Reliability, cost, and the path to 1,000 layers
Each additional 100 layers adds incremental reliability work on program/erase cycling, data retention, and wordline-to-wordline interference, with no single dominant failure mode above 300 layers [S1][S5].
Capacity-per-die, not raw transistor count, drives SSD cost down: a near 3x layer count increase at the same horizontal footprint lets Samsung fit more terabytes per package or shrink the die count required for a given SSD capacity [S2]. The 1,000-layer target, sketched by Lam and ACM Research as a 500 to 1,000 layer direction, depends on string-stacking being extended to three or four tiles rather than two, with hybrid bonding yield and overlay accuracy becoming the gating metrics [S1][S2].
Trackable signals into 2027
Three milestones to watch between now and end of 2027: Samsung's 10th generation 400-layer V-NAND volume ramp during 2026, the 11th generation V-NAND launch in 2027 with a stated 50% I/O rate uplift, and any 500+ layer monolithic or string-stacked announcement from SK hynix or Solidigm to close the gap with Samsung's 900-layer research die [S2][S4].
Secondary signals include the first commercial PLC product, which would shift the bits-per-cell axis independently of layer count, and the JEDEC update cycle for the NVMe and ONFI interfaces that govern how a 1,000-layer die actually talks to a host controller [S1][S5].
Spec-level background on the components involved: 3d scanner, pressure transmitter, and flow meter.
See also our earlier report, Best Shrink Wrapping Machines for Food and Beverage: 2026 Spec Map.