NVIDIA's share of the AI accelerator market by revenue sits at roughly 80% in 2026, with custom hyperscaler ASICs projected to capture 27.8% of AI server shipments, up 44.6% year-over-year, while GPUs grow 16.1% [S1][S2][S5].
The split is sharpest in inference: ASIC inference silicon now targets 10-15% of accelerator spend, AMD merchant GPUs sit at 5-8%, and the residual merchant share fights for what hyperscalers do not internalize [S1][S8].
Inference silicon: GPU still 80%, but the growth curve is splitting
The 2026 GPU revenue share inside AI inference is projected at 35.32%, with the edge inference segment accounting for 70.76% of the inference market by deployment volume [S3]. That gap between revenue share and shipment share is the single most important number for buyers: it confirms GPUs earn more per chip, while ASICs ship in higher unit counts at lower average selling price.
AMD's MI355X is the closest merchant challenger at $8,550 cost, $25,000 sell, and 65.8% margin on TSMC N3P/N6 [S1]. Those margins are why the merchant share is sticky even when hyperscalers internalize more silicon.
Custom ASICs: the 44.6% growth story behind the 80% GPU headline
TrendForce data tracked by multiple outlets shows hyperscaler AI ASICs growing 44.6% year-over-year in 2026 against 16.1% for GPUs, with ASIC-based AI server shipments reaching 27.8% of total shipments [S2][S5]. Google TPU, AWS Trainium 2, Microsoft Maia 100/200, and Meta MTIA v2 are the four named hyperscaler programs; the four together account for 11-18% of 2026 accelerator spend, with Google TPU alone inside the 5-7% band [S1][S5].
On economics, Broadcom reference designs and Marvell co-design partnerships are the dominant external fabless paths for hyperscaler ASIC silicon, with most of the named programs sourced through TSMC N3 or N5 class nodes [S5]. The economic case is simple: a fixed ASIC design amortized over billions of queries for one model architecture beats a flexible GPU on cost-per-token, even after the $20-50 million mask-set and the 12-18 month design cycle [S2]. NVIDIA's December 2025 $20 billion Groq inference-licensing deal was a defensive response to that math, not a counter-strategy [S2].
Decision matrix: GPU, merchant ASIC, custom ASIC, FPGA
For 2026, the four silicon paths line up on four selection criteria. GPU (NVIDIA H100/B200, AMD MI300X/MI355X): 75-87% revenue share depending on segment, $25,000-$65,000 per chip, dominant for training and multi-model inference, software stack (CUDA, ROCm) is the moat [S1]. Merchant ASIC (Groq LPU, SambaNova RDU, Cerebras wafer-scale): unit volume is small, but cost-per-token for stable transformer inference is the headline metric; best for customers with one model architecture at high query volume [S4]. Custom hyperscaler ASIC (Google TPU, AWS Trainium 2, Microsoft Maia, Meta MTIA): 27.8% of AI server shipments in 2026, internal use only, no merchant sales, and the fastest growing segment at 44.6% YoY [S2][S5]. FPGA (Xilinx Alveo, Intel Agilex): smallest share of the four, best for ultra-low-latency inference and reconfigurable pipelines, but losing ground to ASICs as model architectures stabilize [S4][S6].
The matrix below is the working spec for any 2026 inference procurement: GPU wins training, multi-model flexibility, and a mature toolchain; merchant ASIC wins single-model inference at scale where cost-per-query is the line item; custom hyperscaler ASIC is not a procurement option for non-hyperscalers; FPGA holds a narrow edge latency niche. If you can name the model architecture 12 months in advance and your query volume exceeds ~10 billion tokens per month, ASIC economics beat GPU by 2-5x on cost-per-token; below that threshold, GPU utilization wins on flexibility [S2][S4].
Where the silicon actually ships: 27.8% of AI server units, not 27.8% of dollars
Shipment share and revenue share diverge sharply in 2026. ASIC-based AI servers are projected at 27.8% of unit shipments; GPUs are projected at roughly 35.32% of inference market revenue and 45-50% of total AI chip revenue across training and inference combined [S3][S5][S7]. Reading those numbers together: hyperscaler AI ASICs are projected to grow 44.6% in 2026 versus 16.1% for GPUs, yet NVIDIA's GPU revenue share remains at 75-87% of the AI accelerator market by revenue, peaking at 87% in 2024 [S1][S2].
GPUs can also represent roughly 60% of AI server system cost in a high-end build, which is the structural reason hyperscalers keep internalizing silicon at the 44.6% pace [S8]. NVIDIA data center revenue is projected at $150 billion on a $200+ billion total AI accelerator market, down from 87% peak share in 2024 to 75% in 2026, but still larger in absolute dollars than every custom ASIC program combined [S1].
Selection criteria: who each path is for
GPU is for teams running mixed training and inference workloads, multiple model architectures per quarter, or any workload that touches the CUDA, ROCm, or PyTorch/XLA toolchain. The 288 GB HBM3e capacity on the AMD MI300X, the 80 GB on the H100 SXM, and the higher memory bandwidth on the B200 are the differentiators for large-context inference [S1][S6]. Merchant ASIC is for inference-only deployments with one or two model architectures and predictable query volume, where the 12-18 month design cycle can be planned [S4]. Custom hyperscaler ASIC is not a procurement option; it is a strategic in-house build, and only Google, AWS, Microsoft, and Meta operate at the scale that justifies the $20-50 million non-recurring engineering cost per design [S2][S5]. FPGA is for sub-10 ms tail-latency inference where reconfigurability matters more than peak throughput [S6].
Limitations, failure modes, and what to watch
Three failure modes dominate the 2026 inference silicon landscape. First, ASIC design lock-in: a custom ASIC designed for a transformer architecture that gets superseded by a state-space or mixture-of-experts model loses its efficiency advantage, and the $20-50 million mask-set plus 12-18 month design cycle cannot be undone [S2][S4]. Second, GPU supply allocation: NVIDIA controls roughly 80% of TSMC CoWoS packaging capacity, and merchant buyers outside the top four hyperscalers remain allocation-constrained even in 2026 [S1]. Third, software moat erosion: AMD's MI355X offers 288 GB HBM3e at $25,000, undercutting the H100 SXM on memory capacity and price, but ROCm software maturity still trails CUDA for production inference, and that gap is the binding constraint on merchant share [S1][S6].
Trackable signals for the next two quarters: quarterly NVIDIA data center revenue against the $150 billion 2026 line, AMD MI355X hyperscaler design-win announcements, and any second-wave custom ASIC tape-outs from Meta MTIA v2 or Microsoft Maia 200 [S1][S5]. For related reading on the wafer-to-rack supply chain that gates all four silicon paths, see the AI accelerator supply chain map; for the rack-level chokepoints that determine GPU versus ASIC lead times, see the four chokepoints gating AI server-rack buildouts in 2026.
Spec-level background on the components involved: pressure transmitter, flow meter, and industrial valve.