HBM is a 3D-stacked DRAM defined by JEDEC JESD235 and the updated JESD235A, using through-silicon vias (TSV) and a 1024-bit wide I/O to push per-stack bandwidth from 128 GB/s in HBM1 toward 512 GB/s–1 TB/s in HBM2-class devices [S3].
The HBM value chain runs from upstream silicon (DRAM die fab, TSV processing, interposer, and advanced packaging) into downstream GPU, AI accelerator, networking-ASIC, and HPC system-in-package (SiP) integrators, with pseudo-channel and stack-height choices cascading into the final product's memory capacity ceiling [S3][S2].
HBM1 vs HBM2 Spec Tier: Interface Width, Data-Rate, and Stack Height
The original JESD235 HBM1 standard defines a 1024-bit interface running up to 1 Gb/s per pin, with stacks of two, four, or eight DRAM dies on a base logic die and two 128-bit channels per die, giving up to eight independent 128-bit channels per KGSD (known good stacked die) [S3]. Each channel behaves as a 128-bit DDR interface with 2n prefetch, 256 bits per read or write access, and 8 or 16 banks per die, with channel-level independence that lets integrators parallelise traffic [S3].
JESD235A HBM2 keeps the 1024-bit interface, the 128-bit channel structure, 1.2 V core and I/O, and 2Hi/4Hi/8Hi stack options, but raises per-die density to 8 Gb and pushes per-pin data-rate to 1.6 Gb/s or 2 Gb/s, with 8/16/32 GB stack capacity and 512 GB/s–1 TB/s aggregate bandwidth on flagship GPU SiPs [S3]. HBM2 also adds Pseudo Channel mode, which splits each 128-bit channel into two sub-channels so the DRAM can return data more often and lift effective utilisation [S3].
Upstream Supply Chain: DRAM Die, TSV, Interposer, and KGSD Yield
Upstream of the SiP integrator, the HBM chain starts with a DRAM fab (SK Hynix, Samsung, and Micron as the only commercial sources at the time of the HBM2 spec ratification), then a TSV and stacked-die process that bonds two to eight thinned DRAM dies on a base logic die and tests the result as a KGSD before shipment [S3]. The KGSD is then placed on a passive silicon interposer alongside the host die (GPU, AI accelerator, or networking ASIC), and the interposer carries the wide 1024-bit HBM interface across to the host [S3].
Open-source tooling tracks the same dependency tree: the ramulator DRAM simulator fork adds HBM2 and a hybrid-memory model on top of its HBM baseline, exposing the same channel-and-bank timing parameters that the JESD235A spec defines [S2]. That toolchain matters because HBM timing, bank count, and pseudo-channel behaviour are the exact variables that upstream KGSD validation and downstream SiP signal-integrity work both have to respect [S2][S3].
Downstream Integrators: GPU, AI Accelerator, and Networking-ASIC SiPs
The first wave of HBM1 production went into AMD's Fiji SiP and the Radeon R9 Fury / R9 Nano cards, with 4 GB VRAM and 512 GB/s of bandwidth per board, more than enough for 2016-class graphics but a clear ceiling for anything larger [S3]. HBM2 lifted that ceiling to 8/16/32 GB stacks and 512 GB/s–1 TB/s per stack, which is the band the upcoming AMD and NVIDIA video cards of that generation were designed against [S3].
Beyond discrete GPUs, the downstream set now spans AI-training accelerators, HPC SiPs, and high-end networking ASICs, all of which need the wide 1024-bit interface, the 2n prefetch, and the independent 128-bit channels to feed their compute pipelines [S3]. The OpenVINO toolkit merged HBM memory support in 2025, formalising HBM as a target memory for inference workloads and confirming the AI-accelerator downstream pull that drives upstream capacity allocation [S1].
Decision Criteria for HBM Selection: Bandwidth, Capacity, Power, and Stack Height
Four parameters govern the HBM selection: per-pin data-rate (1 Gb/s for HBM1 vs 1.6–2 Gb/s for HBM2), per-die density (up to 8 Gb in HBM2 vs 2 Gb in early HBM1), stack height (2Hi/4Hi/8Hi in both generations), and the channel architecture (eight independent 128-bit channels per stack, with pseudo-channel as an HBM2-only option) [S3].
For AI training and HPC SiPs, the dominant lever is aggregate bandwidth per stack, which is why HBM2 at 1.6–2 Gb/s per pin and 8/16/32 GB capacity became the baseline for the 512 GB/s–1 TB/s class parts [S3]. For cost-sensitive or capacity-light edge inference, the same HBM2 spec allows smaller 4Hi stacks with pseudo-channel mode, trading peak throughput per channel for higher effective utilisation [S3]. Downstream buyers should also confirm pseudo-channel support in the host controller and the memory-controller timing model, since the ramulator-style simulators expose that behaviour directly [S2].
Limits, Failure Modes, and Sourcing Risks in the HBM Chain
Upstream, the HBM chain is constrained by TSV yield on 8Hi stacks, by interposer availability, and by KGSD test coverage, because a single weak die in an 8Hi stack can fail the whole stack and waste the host SiP [S3]. Downstream, the wide 1024-bit interface and the 1.2 V I/O demand tight signal-integrity work on the interposer, and any channel that loses timing margins will cap the SiP at the slowest channel rather than the aggregate spec [S3].
Open-source simulators carry those limits forward: ramulator exposes the HBM1 and HBM2 timing, bank, and channel parameters that downstream memory controllers must hit, and the HBM2 + hybrid-memory fork is a working example of how to model stacked DRAM with pseudo-channel on top of a baseline HBM model [S2]. For sourcing decisions in 2026, see the HBM allocation and CoWoS map, which is the most directly relevant downstream guide to where the upstream TSV and interposer capacity is actually landing in SiP builds.
Standards, Tools, and Trackable Signals
The governing documents are JEDEC JESD235 (HBM1) and JESD235A (HBM2), which together fix the 1024-bit interface, 2n prefetch, 128-bit channel structure, 1.2 V core and I/O, 2Hi/4Hi/8Hi stack options, and the HBM2 pseudo-channel mode [S3]. Engineering-side, the ramulator DRAM simulator and its HBM2 / hybrid-memory fork give a cycle-accurate model of those exact parameters and are the de-facto reference for memory-controller validation [S2]. On the software side, OpenVINO merged HBM memory support in 2025, putting HBM into the inference toolchain alongside the GPU and accelerator SiPs that consume it [S1].
Trackable signals to watch: further OpenVINO HBM memory PRs landing on master, ramulator timing-model updates that add post-HBM2 channel modes, and any JEDEC activity beyond JESD235A. Downstream, the AI-cluster liquid-cooling shift is the leading indicator of how HBM-heavy SiPs are being deployed at rack scale, since 512 GB/s–1 TB/s stacks drive the same thermal envelope that direct-liquid-cooling designs now address.
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