Global semiconductor lithography equipment revenue is forecast at USD 30.44 billion in 2026, climbing to USD 47.63 billion by 2031 on a 9.37% CAGR [S1]. A separate forecast places 2026 spend at USD 32.16 billion reaching USD 67.43 billion by 2034 at 9.70% CAGR [S4], while a third pegs the year at USD 31.55 billion with a USD 66.31 billion 2034 endpoint at 9.73% CAGR [S3].
Deep ultraviolet (DUV) systems still own 67.31% of 2025 market share by lithography type, while High-NA EUV is the fastest-growing slice at 10.12% CAGR through 2031 [S1]. Asia-Pacific captures 63.58% of 2025 revenue, and North America is the fastest-growing region at 10.33% CAGR [S1]. For context on how this kind of capital-equipment market shapes adjacent process-control purchases, see the solid-state battery process control map for a parallel capex pattern.
Technology Mix: DUV Floor, EUV Ceiling, High-NA Ramp
DUV remains the volume base in 2026 because ArF immersion, KrF steppers, and i-line tools still cover the 28-180 nm node range used in power, automotive, and MEMS devices [S1][S4]. 300 mm wafers dominate with 72.67% of 2025 share; the 450 mm transition is forecast at 9.91% CAGR but has not broken out as a real installed base [S1].
EUV and High-NA EUV are the capex story. ASML's EXE:5000 platform uses a 0.55 numerical aperture and is being qualified for sub-2 nm logic and high-bandwidth memory [S4]. Intel's 2026 filings indicate that Intel 18A will absorb a growing share of production at Fab 52 (Chandler, Arizona) using EUV, with Intel 14A designed to potentially incorporate High-NA EUV in high-volume logic manufacturing [S4]. Across the wider fab equipment book, lithography alone accounted for 36% of the total USD 138.64 billion semiconductor equipment market in 2025 [S5], confirming photolithography's position as the single largest capex line item.
Application and End-User Split
Advanced packaging is the largest single application in 2025 at 36.74% of lithography revenue, reflecting the shift to 3D heterogeneous integration and large-panel formats; R&D prototyping grows fastest at 10.39% CAGR through 2031 [S1]. Pure-play foundries are the dominant end-user at 46.89% of 2025 share, with OSAT providers posting the fastest 9.96% CAGR [S1].
Automotive electrification drives an estimated 80% of current vehicle electronics innovation, which in turn pulls DUV tool demand at mature nodes where cost-per-wafer, not resolution, is the deciding metric [S3]. Memory and logic both remain exposure-tech constrained: high-bandwidth memory stacks for AI accelerators now require EUV-class overlay accuracy that i-line and KrF steppers cannot deliver, pushing memory IDMs into the same tool pool as logic foundries.
Vendor Map: ASML Plus Three Challengers
The 2026 named players are ASML Holding N.V., Nikon Corporation, Canon Inc., EV Group, Veeco Instruments Inc., SUSS MicroTec SE, Shanghai Micro Electronics Equipment (SMEE), Neutronix Quintel, JEOL Ltd., and Onto Innovation [S4]. In practice the wafer-stepper and scanner market is a four-vendor core: ASML, Nikon, Canon, and SMEE, with the remainder addressing mask aligners, nanoimprint, advanced packaging lithography, and metrology adjacencies [S3][S4].
ASML is the only producer of EUV and High-NA EUV production scanners, and the only vendor with a 0.55 NA system in customer qualification [S4]. Nikon and Canon compete in ArF immersion, KrF, and i-line steppers, with Canon's FPA-3030i5a i-line platform targeted at compound semiconductor and power-device lines [S3]. SMEE (Shanghai Micro Electronics Equipment) is the domestic Chinese alternative, listed in both the named-player roll and the MtM (More than Moore) growth narrative [S3][S4]. EV Group, Veeco, and SUSS MicroTec address the nanoimprint, wafer-bonding, and advanced-packaging lithography segment that is no longer a secondary line item.
Decision Criteria: EUV vs DUV vs Advanced-Packaging Lithography
Three tool classes are now on every capex shortlist. Pick by node, wafer size, and panel format, not by brand. Use the comparison below to frame sourcing decisions. [S3]
EUV (0.33 NA) and High-NA EUV (0.55 NA) target sub-7 nm logic and 1y/1z nm DRAM, with single-exposure High-NA cuts flow steps but requires new optics, pellicle, and reticle-handling capex; throughput in High-NA is still ramping at customer sites [S4]. DUV ArF immersion covers 28-7 nm with multi-patterning, holds the lowest cost-per-wafer for mature logic, power, and automotive, and represents 67.31% of 2025 share [S1]. Advanced-packaging lithography (steppers, mask aligners, digital lithography, and nanoimprint tools) addresses fan-out wafer-level packaging, 2.5D/3D stacking, and large-panel formats; it is now 36.74% of 2025 application revenue and is the second-fastest application growth line [S1].
Decision rule used in 2026 sourcing: if the wafer is 300 mm and the node is 7 nm or below, EUV or High-NA EUV is mandatory. If the wafer is 200/300 mm at 28-180 nm, DUV ArF immersion or KrF is the cost-optimum. If the line is bumping, fan-out, or hybrid bonding, stepper or mask-aligner capacity is the constraint, not resolution [S1][S4].
Demand Drivers and Constraints in 2026
Five forces carry 90% of the demand uplift. Process-node shrinkage adds +2.6% to CAGR, AI and data-center demand adds +2.3%, CHIPS and EU Chips Act subsidies add +1.7%, 3D heterogeneous integration adds +1.4%, and metal-oxide photoresist adoption below 2 nm adds +0.5% [S1]. EUV pellicle commercialization is a small but near-term driver at +0.3%, concentrated at leading-edge fabs [S1].
Constraints are equally concrete. Lithography is the largest single tool-line capex, and supply-chain concentration in EUV sources, photoresists, and optical components caps how fast any one region can ramp. Geopolitical bifurcation is forcing suppliers to maintain separate compliance paths for China and for the CHIPS Act geography, fragmenting the customer book [S1]. The Mordor driver-impact table is also explicit that advanced packaging, not front-end scaling, is the long-term (4+ year) tailwind, with Asia-Pacific as the core and North America and Europe as the spillover zones [S1].
Selection Cues for Process Engineers
Specification should be driven by the wafer, the node, and the package. For leading-edge logic, qualify the EXE:5000 (0.55 NA) and lock source-power service contracts early, since EUV source uptime dominates cost-of-ownership. For mature-node and automotive lines, specify ArF immersion or KrF tools with overlay below 2 nm and throughput above 200 wafers per hour; DUV cost-per-wafer still wins at 28 nm and above. For advanced packaging, prioritize large-panel steppers and mask aligners with overlay below 1 µm and 2.5D/3D stacking compatibility, not raw resolution [S1][S4].
For buyers facing capex allocation between capex-intensive lithography and adjacent metrology, the same 2026 capex discipline that shapes smart-meter procurement roadmaps applies: lock multi-year service, qualify a second source, and price the option of SMEE or Canon for non-leading-edge lines. EV Group, Veeco, and SUSS MicroTec remain the named suppliers for the advanced-packaging lithography sub-segment, with competition pivoting on overlay accuracy, throughput, and packaging-format flexibility [S4].
Trackable signals into late 2026 and 2027: ASML High-NA EXE:5000 production-volume disclosures, Intel 14A High-NA integration milestones at Arizona and Ohio sites, and any SMEE SSA-800-series EUV progress at domestic Chinese foundries [S4]. Watch also for the next round of CHIPS Act pre-construction tool reservations, since lithography is the line item that locks fab capex first.
Component reference pages worth checking: ndt equipment, anti static equipment, and construction machinery and equipment.