Lithography equipment demand through 2030 rides on a stacked set of macro numbers: Gartner projects 2026 worldwide semiconductor revenue above $1.3 trillion [S1], while SEMI's March 2026 outlook sizes total wafer-fab equipment (WFE) at $145B in 2026 rising to $156B in 2027 [S4]. Lithography is a structural share of that pool, anchored by extreme-ultraviolet (EUV) systems at the leading edge and deep-ultraviolet (DUV) tools at mature nodes.
Advanced packaging has become the second engine. PatSnap's 2026 landscape puts the segment at roughly $37.4B in 2021, tracking a 74% surge to $65B by 2027, with packaging's share of total semiconductor packaging climbing from ~40% (2020) to >60% by 2030, and equipment sales in this slice already growing >10% in 2024 and >20% in 2025 [S2]. That mix shift is reallocating tool demand across lithography, bonders, and inspection rather than shrinking it.
Macro sizing: 2026 revenue, 2026-2027 WFE, and what 2030 implies
Process engineers reading the 2026 capex cycle should anchor on three reference points. Gartner's 8 April 2026 release calls worldwide semiconductor revenue above $1.3 trillion in 2026, a more-than-50% jump, with AI accelerators (GPUs and adjacent logic) named as the dominant demand vector [S1]. SEMI's 18 March 2026 WFE forecast reads $145B (2026) and $156B (2027), driven by AI scaling and packaging complexity, with test equipment also in an upcycle [S4]. Markets.com's 19 August 2026 stock brief cites the leading lithography supplier's Q2 2026 release of €9.3B in net sales and a raised full-year outlook, a useful leading indicator of EUV tool shipment cadence [S3].
By 2030, the mix looks different. With packaging's share of the total semiconductor packaging market projected above 60%, and AI server demand still lifting tool orders, the lithography book of business is best modelled as two blocks: leading-edge EUV (where throughput, NA, and source power dominate the spec) and mature-node DUV/ArF-i (where cost per wafer and uptime dominate). For adjacent capital categories that pull on the same fab footprint, see the construction machinery and equipment spec map for cleanroom build-out context, and the lighting equipment and electric lamps spec map for the yellow-room illumination constraints that gate photoresist handling.
Demand drivers: AI accelerators, HBM, and advanced packaging pull-through
AI is the single largest pull on lithography demand through 2030. The Gartner 2026 outlook explicitly cites AI accelerators (GPUs and adjacent logic) as the engine behind the >50% revenue jump [S1], and HBM stack height plus 2.5D/3D integration are the packaging-side multiplier [S2]. Hybrid bonding has reached commercial mass production at 9μm pitch (AMD 2nd-generation 3D V-Cache: 7nm SRAM stacked face-to-back on 5nm logic, a 10× bandwidth gain over conventional packaging), with R&D pushing toward 2-5μm pitch on Cu/polymer hybrid bonders [S2]. Each hybrid bonder on a packaging line reduces but does not eliminate the litho burden, because the through-silicon via (TSV), redistribution layer (RDL), and microbump under-bump metallization still step on DUV scanners.
The equipment-sales numbers confirm the speed of that pull. Advanced-packaging equipment grew >10% in 2024 and is tracking >20% in 2025 [S2], which is the kind of step change that resets lithography order books 6-12 months downstream. Process specifiers who want to see the AI capex flow represented in a buyable catalog should look at adjacent categories like flow meter selection for high-purity gas and chemical delivery and pressure transmitter wiring for vacuum and gas-panel loops, both of which scale with new fab and advanced-packaging line builds.
Selection criteria by application: EUV vs DUV vs packaging litho
The decision tree splits cleanly by node and use case. At the leading edge, EUV and High-NA EUV are the only credible routes to sub-3nm logic and 1γ/1δ DRAM, so specifiers should compare tools on numerical aperture (0.33 NA vs 0.55 NA), source power (in the multi-hundred-watt class for production EUV), wafer-per-hour throughput at production dose, and overlay budget. At mature nodes (28nm and above) and for analog/power/RF, ArF-immersion and KrF scanners dominate, and the right spec axis is cost per wafer, mask count, and matched-machine overlay across a multi-tool fleet. For advanced packaging, litho is increasingly about RDL, Cu-pillar, and TSV reveal steps, where panel-format steppers and i-line/KrF tools are the workhorses. [S2]
For factory-floor tooling adjacent to lithography bays, ESD discipline ties to anti-static equipment selection, and the metrology that gates overlay control rides on NDT equipment choices for inline defect and film-thickness verification. The comparison below lines the three lithography regimes up against the four criteria a 2026 process-engineering team actually grades on.
Standards, sourcing, and spec discipline
Lithography procurement in 2026 lives under a tighter compliance net than five years ago. End-use export controls (US EAR / Entity List, EU dual-use, Japan METI, Netherlands foreign-export rules on advanced steppers) gate both which tools can ship cross-border and which fabs can accept them, so any 2026-2030 demand forecast has to carry a country-mix overlay. On the equipment side, process specifiers should anchor to ISO 9001 quality systems for the tool builder, ISO 14001 for fab environmental management, and SEMI E10/E12/E48 for equipment automation and reliability definitions; on the process side, the ITRS/IRDS lithography roadmap chapters are the reference for node-level overlay, CD, and defect-density targets, and SEMATECH-derived defect-reduction guidance applies for high-NA EUV introduction. These are baseline checks, not differentiators. [S3]
Sourcing posture is equally concrete. With SEMI's WFE at $145B in 2026 and $156B in 2027 [S4], and the leading lithography supplier raising its full-year 2026 outlook after a €9.3B Q2 print [S3], lead times on EUV systems remain multi-year, and a second-source strategy at the EUV level is not commercially available. The realistic hedge is to lock DUV capacity early, qualify multiple DUV suppliers, and pre-book service contracts, which is the same playbook that semiconductor-analyst coverage flagged as a 2026 risk theme [S3]. For a wider look at how AI-driven capex is reshaping adjacent capital categories, the solar inverter procurement spec map reads the same way: FEOC rules and lead-time discipline now drive the buy.
Constraints and failure modes a 2030 forecast must price in
Three constraints will decide whether the 2026-2030 litho demand curve is steep or flat. First, EUV source power and pellicle maturity gate High-NA EUV ramp; if 0.55 NA systems stay below ~150 wafers per hour at production dose, the 2nm/1.4nm capacity curve flattens and multi-patterning DUV re-enters. Second, advanced-packaging line build pace determines how fast the >20% 2025 packaging-equipment growth rate [S2] translates into bonding-area lithography orders, because RDL and microbump steps scale with hybrid bonder installations. Third, export-control churn, especially around leading-edge EUV, can swing a national fab's tool receipt date by 6-18 months, which the 2026 analyst coverage treats as a first-order risk [S3].
Failure modes for the tool base itself are well understood: pellicle defectivity, mask-blank availability, and reticle-handler uptime have historically been the three top yield-limiters on EUV, while DUV fleets tend to fail on chiller, laser, and projection-optics contamination. A spec-side hedge is to require a documented mean-time-between-assist (MTBA) target and a guaranteed service-level agreement (SLA) on consumable throughput per wafer pass, both of which the SEMI E10/E12 reliability vocabulary already defines.
Who this demand wave is for, and who it is not for
This capex wave is for foundries, IDMs, and advanced-packaging OSATs that are already on the EUV or hybrid-bonding roadmap, and for the equipment suppliers, gas-and-chemical vendors, and facility builders that serve them. It is not for greenfield entrants trying to bypass the learning curve at 3nm and below, where the EUV tool cost, multi-patterning mask count, and yield ramp make a clean-sheet fab uneconomic against the existing leading-edge foundry footprint. Mid-tier analog, power, RF, and MEMS fabs will see steady DUV and i-line demand, but not the step change that AI-logic and HBM lines will absorb. [S2]
Trackable signals to watch over the next four quarters: SEMI's quarterly WFE updates (next major refresh expected alongside SEMICON), the leading lithography supplier's quarterly order intake versus backlog conversion, and the advanced-packaging equipment quarterly growth rate as a leading indicator of RDL/TSV lithography pull-through. If any of these soften, the 2027 WFE number is at risk before 2030 mix-shift assumptions are.