Across a 2026 cost build for a discrete power MOSFET or IGBT, the wafer-fab process step — epitaxy, lithography, implant, etch, metallisation, passivation — still consumes the largest share of the per-die cost, while back-end packaging and final test together rival it on absolute dollars once copper-clip, silver-sinter, or clip-bond SiC modules enter the bill of materials [S1].
Cost drivers differ sharply by device family: a 650 V SiC MOSFET wafer costs several times the equivalent silicon super-junction wafer area, and the dicing step alone on a thin SiC substrate pushes kerf loss and blade-wear above the silicon baseline. Production-test capital, particularly dynamic RDS(on) and short-circuit test capability for wide-bandgap devices, is now a gating line item rather than a sunk overhead [S2][S3].
Wafer fab cost: epi, lithography, and SiC/Si premium
Wafer fabrication cost for a power device is governed by die area, wafer diameter, process-node complexity, and — for SiC — the epi-reactor cost-of-ownership plus the boule-substrate premium that runs 5–10× equivalent silicon wafer cost per unit area [S1]. A 150 mm SiC wafer, the workhorse for 650–1700 V MOSFETs, prices above the 200 mm silicon baseline that the 12-inch silicon power fabs have driven down.
Yield is the multiplier: a 70% vs 90% sort yield on a thin-wafer SiC line changes cost-of-goods by 20–30% before the part ever reaches package. Front-end test (wafer-probe) on production probers like the ACCRETECH probing-machine line filters known-good dies before dicing, and that step protects back-end yield economics where a single bad die in a multi-chip module can scrap a $40 power package [S2].
Packaging cost: clip bond, silver sinter, AMB substrate
For high-current SiC and IGBT modules, the package — not the die — frequently carries the largest single line item. Active-metal-brazed (AMB) silicon-nitride or alumina substrates for 1200 V+ modules run a premium versus the legacy direct-bond-copper (DBC) alumina used in 600 V industrial parts. Silver-sinter die-attach and copper-clip bond wires replace aluminum wire bonds to handle higher current density and thermomechanical stress; the consumable silver content alone can move the package cost by 15–25% versus a wire-bonded equivalent [S1].
Throughput on the packaging line is constrained by dicing, die-bond, and wire-bond or clip-bond cycle times. Dicing thin SiC wafers — typically 100–200 µm thick after back-grind — requires precision dicing machines with kerf control and edge-chipping limits that silicon lines tolerate more loosely. ACCRETECH dicing-machine and polish-grinder lines used in production fabs reflect this: back-grind, edge-grinding, and wafer-demounting are treated as separate, yield-critical process steps rather than incidental finishing [S2].
Test cost: dynamic RDS(on), short-circuit, and wide-bandgap overhead
Final test and burn-in for a power device has moved from a low-single-digit share of total cost to a double-digit share once dynamic on-resistance, short-circuit-withstand-time (SCWT), and gate-ringing tests are required for SiC and GaN qualification. Testers like the ipTEST M2 platform — built on the Mostrak production-tester legacy with 30+ years of power-device experience — explicitly target high-speed, broad-coverage parametric testing for GaN and SiC discretes, with a configurable handler interface for both wafer/KGD and final-test production [S3].
Test cost is a function of test time × parallelism × capital amortisation. Wide-bandgap devices with high dV/dt switching and low gate-threshold margins demand longer per-pin test times and tighter guard-bands; ATE throughput per hour is the lever procurement uses to score suppliers, and it shows up in the per-die test cost allocation. Reference instrumentation for the upstream process-control side is covered in a separate spec walkthrough of power semiconductor process-control instrumentation and the QA layer in power-semiconductor FIT and failure-analysis spec work.
Cost-driver comparison across the main device families
Comparing the three dominant cost lines by device family: silicon planar MOSFET keeps wafer cost as the single largest line (≈55–65% of COGS), packaging moderate (≈20–25%), test low (≈5–10%) at mature 200 mm/300 mm super-junction nodes. SiC MOSFET inverts that picture — the SiC epi substrate premium lifts the wafer line to ≈40–50%, AMB/sinter packaging climbs to ≈30–40%, and wide-bandgap-specific test adds ≈10–15% [S1][S3]. GaN HEMT (normally-off, 100–650 V) sits in between on packaging (smaller die, wafer-level chip-scale packages) but pushes test cost up because of dynamic RDS(on) screening, which GaN-on-Si wafers especially demand.
The three decision criteria for a sourcing team are therefore substrate cost (Si vs SiC vs GaN-on-Si), package construction (DBC vs AMB, wire-bond vs clip/sinter), and test coverage class (static-only vs dynamic RDS(on) + SCWT). Each axis moves independently, and a cheaper wafer can be wiped out by a more expensive package, as the capacity-shift write-up on AMB substrates and SiC demand makes concrete.
Where the cost actually moves: 2026 driver stack
Yield and throughput are the second tier: a 5-point yield improvement on a SiC line can swing COGS more than a 10% substrate-price negotiation, which is why back-grind, edge-grind, and dicing consumables like precision dicing blades are treated as yield-critical rather than commodity items [S2].
Volume tier matters as well — fabs running 200 mm silicon super-junction at high utilisation sit at the lowest cost-per-ampere; 150 mm SiC lines still climb the learning curve, and greenfield SiC capacity build-out through 2025–2026 has not yet collapsed the cost gap to silicon baseline. The power-transformer encyclopedia entry is unrelated to the fab step but is a useful cross-reference when the power-conversion downstream of the device sets the cost ceiling the OEM will accept. For facilities planning around similar capital-equipment budgeting discipline, the gear-pump price map uses an analogous cost-driver breakdown framework that transfers cleanly to fab consumables.
Total cost of ownership: amortisation, yield, and test time
Purchase price per die is misleading as a sole figure. A full TCO view includes capital amortisation on the epi reactor and ATE (often a 5–7-year write-off on production testers), consumable cost (dicing blades, probe cards, sockets, test load-board wear), and energy cost per wafer-pass — SiC epi reactors are notably power-hungry, and that kilowatt-hour line shows up in the cost stack at European fab rates. Maintenance and calibration of the production tester line is the third leg: a tester with poor drift on high-voltage measurement channels forces wider guard-bands, which inflates yield loss downstream [S2][S3].
On a 7-year amortisation basis, SiC MOSFET COGS in 2026 still runs multiples of the equivalent silicon super-junction MOSFET, but the gap has narrowed each year as 200 mm SiC wafer supply has tightened into volume and AMB-substrate capacity has ramped. Procurement should score suppliers on the three lines — wafer, package, test — separately, not on a blended cost-per-ampere, because a supplier with a low wafer cost and a high package cost is exposed differently from the reverse profile.
Selection criteria: who pays the premium, and who does not
The SiC premium is justified for traction inverters, on-board chargers, solar string inverters above 50 kW, and industrial drives where the system-level efficiency gain (lower conduction + switching loss) pays back the device premium inside the warranty window. It is not justified for sub-300 V consumer adapters, low-power auxiliary supplies, or cost-down industrial contactors where a silicon super-junction or even a planar MOSFET meets the thermal and efficiency budget at one-third to one-half the device cost [S1].
GaN HEMT hits a different niche — sub-1 kW AC/DC converters, USB-PD adapters, lidar drivers, and D-class audio — where the speed advantage matters and the 100/150 mm GaN-on-Si wafer keeps the substrate line in check. Test cost remains the swing variable: a GaN line that skips dynamic RDS(on) screening ships infant mortality into the field, and the field-failure cost overwhelms the test saving within one model year.
For a 2026 sourcing decision, a power-electronics OEM should score suppliers on four criteria: (1) wafer/substrate cost per ampere rating, (2) package construction and thermal impedance, (3) dynamic-test coverage on the ATE platform, (4) demonstrated field-FIT rate. The fourth metric is the one that closes the loop on the other three, and it is the criterion a power-meter-class metrology discipline would normally enforce upstream of the device datasheet.
Standards and sourcing signals to track
Reliability qualification is anchored in AEC-Q101 for automotive discretes and JEDEC JESD22 for industrial-grade parts, with the test program defining the screen coverage and the ATE capability defining the guard-band cost. A sourcing team that asks only for AEC-Q101 lot-by-lot may over-pay for parts that have already been fully characterised; one that accepts only vendor-generic data without AEC-Q101 evidence takes the field-FIT risk onto its own warranty. Track the supplier's published dynamic-RDS(on) test time per part, the AMB-substrate traceability paperwork, and the ATE platform vintage — older testers force wider guard-bands, which inflate the effective per-die test cost without appearing in the line-item quote [S3].
Two signals to watch into the second half of 2026: 200 mm SiC wafer supply contracts (any new entrant at this diameter moves the cost curve), and dynamic-RDS(on) ATE throughput at tier-1 test houses (capacity there gates the volume ramp for SiC and GaN production). Either of these is a more reliable leading indicator of device cost than headline ASP, and a follow-up reading of the AMB-substrate capacity map gives the supply-side anchor for the wafer and package lines in the breakdown above.
For the relevant spec sheets and selection criteria, see additive manufacturing material.