Three DRAM makers — SK hynix, Samsung Electronics, and Micron Technology — are the only companies shipping High Bandwidth Memory (HBM) at production scale in 2026, with SK hynix leading on HBM3E volume and HBM4 sampling [S3].
The global memory chip market in 2026 is sized at roughly USD 440-550 billion, up about 90% year-on-year, and HBM is the single fastest-growing sub-segment because every AI accelerator class (NVIDIA Blackwell/Rubin, AMD MI400, custom ASICs) requires it [S3]. For a non-specialist, HBM is a 3D-stacked DRAM die family (JEDEC JESD238 / HBM2, JESD238A HBM3, JESD238B HBM3E, HBM4) bonded to a logic die through a silicon interposer or advanced packaging, delivering multi-TB/s class bandwidth per stack [S4]. The article below ranks the players, breaks down what each is shipping, and flags the sourcing risks for buyers.
The 2026 HBM supplier set is an oligopoly of three DRAM IDMs
Only three integrated DRAM manufacturers (IDMs) — SK hynix (KRX: 000660), Samsung Electronics (KRX: 005930, memory division), and Micron Technology (NASDAQ: MU) — control the HBM market, because the stacking, TSV, and advanced-packaging know-how is gated inside the IDM model [S3]. SK hynix is reported as the volume leader on HBM3E and the first to ship HBM4 samples to NVIDIA, Samsung is in qualification cycles for HBM3E at NVIDIA while pushing HBM4 to multiple customers, and Micron is qualifying HBM3E 8-Hi and 12-Hi products with its 1-beta DRAM node [S3]. For background on how HBM stacks compare with conventional DRAM, the HBM memory industry trends 2026: stacked DRAM, JEDEC JESD238B, and mobile HBM roadmap article lays out the standard progression. Chinese entrants — CXMT, ChangXin Memory, and a Wuhan-based project — are publicly named as 2026 HBM aspirants, but none have announced JEDEC-compliant HBM3/HBM3E mass production, so they sit outside the shipping-tier list [S3].
SK hynix: HBM3E volume leader, HBM4 sampling first
SK hynix entered 2026 with the largest HBM3E 8-Hi/12-Hi allocation, supplying NVIDIA Blackwell (B100/B200/GB200) and key custom-ASIC customers, and reportedly cleared HBM4 quality validation for NVIDIA's Vera Rubin platform ahead of the other two [S3]. The 12-layer (12-Hi) HBM3E part delivers roughly 819 GB/s per stack at a 6.4 Gb/s/pin data rate, with 36 GB per stack, and is the SKU that defines 2026 AI-server memory content [S4]. SK hynix also continues to own the foundational patents around the original HBM mass-reflow-based stack-and-through-silicon-via process flow that the other IDMs have since replicated, which is why its qualification cycles run shorter [S4]. For the demand-supply framing that sets the 2026 price/volume curve, the HBM memory market size and 2026 forecast: stacked DRAM demand, supply, and standards brief is the cleanest reference.
Samsung Electronics: HBM3E re-qualifying, HBM4 capacity ramp
Samsung Memory Division is the second 2026 HBM supplier, with HBM3E 8-Hi (32 GB, 6.4 Gb/s/pin) in qualification with NVIDIA after a thermal-design and yield-rework cycle that delayed its 2025 ramp, and HBM4 sampling to multiple non-NVIDIA accelerator customers including AMD MI400 and Google TPU programmes [S3]. Samsung's strategic edge is its full-stack control — DRAM, advanced packaging (I-Cube S / 2.5D, X-Cube / 3D), and foundry access — which lets it offer a packaged HBM-plus-logic tile in a single contract. The risk side is concentrated: a single qualification slip at one hyperscaler pushes hundreds of millions of dollars of 2026 revenue into 2027. Buyers specifying Samsung HBM should anchor the contract on JEDEC JESD238B HBM3E conformance, not vendor-private mode-set extensions.
Micron Technology: HBM3E 12-Hi at 1-beta, smaller share but qualified
Micron is the third HBM supplier in 2026, with HBM3E in 8-Hi (24 GB) and 12-Hi (36 GB) versions qualified by NVIDIA for both Blackwell and earlier Hopper SKUs, built on the company's 1-beta DRAM node and shipped from its Hiroshima facility [S3]. Its 2026 HBM revenue share is materially below SK hynix's but above any non-IDM entrant, and Micron has been transparent that 2026 HBM bit-supply growth is sold out under LTAs (long-term agreements) with multiple AI customers. The operational lever Micron offers buyers is geographic diversification: Japan-based front-end and US packaging mean its HBM3E is the politically preferred second source for some US hyperscaler procurement policies. Where a buyer needs to pin a per-stack bandwidth and capacity figure, the HBM memory industry trends 2026 page gives the JEDEC JESD238B numerical anchors.
HBM is not commodity DRAM — and not a fit for every workload
HBM is a JEDEC-defined, advanced-packaging-bound memory tier — it is not interchangeable with DDR5, GDDR7, or LPDDR5X, and it is not a drop-in for general-purpose servers [S4]. The form factor is a 2.5D-stacked DRAM-on-interposer or a 3D-stacked logic-die-bonded device that must be co-designed with the host ASIC's PHY, thermal envelope, and substrate. For industrial control and PLC work — where deterministic latency, long product lifecycles, and 4-20 mA / HART-style I/O are the norm — a pressure transmitter, flow meter, or industrial valve subsystem does not use HBM at all, and an industrial PLC running ladder logic on an 8-bit MCU does not need it. HBM only makes engineering sense inside an AI accelerator, a high-end integrated GPU package, or a networking ASIC that must move multi-TB/s into a compute die. Buyers who ask for HBM outside that envelope are usually paying for bandwidth they cannot use.
Standards, sourcing risks, and trackable 2026 signals
The HBM roadmap runs on JEDEC: JESD238 (HBM2), JESD238A (HBM3), JESD238B (HBM3E), and the in-flight HBM4 standard, which fixes the per-pin data rate, channel count, and stack-height envelope that all three IDMs conform to [S4]. 2026 sourcing risks are (1) NVIDIA-driven allocation — SK hynix, Samsung, and Micron all prioritise the largest GPU customer first, (2) advanced-packaging capacity (CoWoS-L, SoIC) that bottlenecks HBM bit volume more than the DRAM wafer output itself, and (3) geopolitical exposure of Korean DRAM nodes for any China-restricted end-use. Trackable 2026 signals to watch: (a) HBM4 mass-production timing at each of the three IDMs, (b) any non-IDM entrant reaching JEDEC-compliant HBM3E sampling, and (c) the JEDEC HBM4 publication date, which sets the spec ceiling every accelerator roadmap in 2027 will be written against.