ASML's CFO confirmed a 2026 plan to ship more than 60 Low-NA EUV systems, roughly 25% above 2025 volume, with about 10 High-NA EXE:5200B scanners layered on top at a list price near $380–400 million each [S1][S6]. The split matters: every High-NA unit consumes ASML capacity that could otherwise feed Low-NA, and the High-NA ramp is now the swing variable in fab capex allocations through 2027.
The High-NA unit cost, the wafer throughput gap versus Low-NA, and the multi-patterning penalty avoided at 14A/A14/A16 nodes are the three numbers any process engineer should hold when comparing a 0.33-NA versus 0.55-NA roadmap. Standard EUV runs 0.33 numerical aperture with 13.5 nm light, while ASML's High-NA EXE platform shifts to 0.55 NA optics, improving resolution and contrast so that transistor pitches around 1.7x smaller and densities up to 2.9x higher than the prior NXE generation become printable in fewer exposure steps [S5].
Shipment Mix and the Q1 2026 Service Line That Tells the Real Story
ASML's Q1 2026 net sales reached €8.8B, up roughly 13% year over year, and the installed base management segment posted €2.5B (around 25% YoY growth) [S1]. That services number is more diagnostic than the systems number: it shows fabs are paying to extract throughput from existing NXE:3800E tools via field upgrades and performance options before new Low-NA slots arrive, and it implies that EUV system sales of about €4.1B (roughly 65% of system revenue) included only two High-NA recognitions that quarter.
Q4 2025 bookings hit a record €13.2B, a figure that, with the typical 12–18 month revenue recognition lag, locks in delivery tail well into 2027 and into 2028 for late-acceptance systems [S1]. CEO Christophe Fouquet's framing, that "demand for chips is outpacing supply," signals a constraint that has migrated upstream past wafer-foundry capacity into the EUV source, optics, and reticle infrastructure that ASML itself must source on long lead times [S1]. The full-year 60+ Low-NA target is the largest single-year EUV shipment commitment in ASML's history and stresses that upstream supply chain in a way no prior year has.
High-NA vs Low-NA EUV: Decision Criteria for Process Engineers
High-NA EUV (EXE:5000, EXE:5200B) uses a 0.55 NA anamorphic optic and reaches roughly 8 nm resolution in single exposure, versus the 0.33 NA NXE:3800E that delivers around 13 nm in a single pass and relies on multi-patterning for sub-7 nm metal and via layers [S5]. The High-NA selling point is fewer exposure steps per critical layer; the catch is throughput, mask infrastructure, and the $360–400 million per tool price tag that has cooled every buyer except Intel [S2][S5].
Four criteria separate the platforms cleanly: cost per layer, mask blank readiness, stitching risk, and HVM ramp timing. Low-NA EUV is the proven workhorse with a deep mask and resist ecosystem, and TSMC plans to extend it through A14 (1.4 nm) and A16 (1.6 nm class) via multi-patterning rather than absorb the High-NA capex shock [S3]. High-NA collapses multi-patterning steps and lifts resolution, but the anamorphic field forces stitching at chip boundaries, an engineering problem that until September 2026 was still considered open at HVM scale [S4]. Engineers building a 14A or 10A roadmap should weigh: (1) will your critical layers tolerate stitched exposure, (2) is your mask blank supply qualified for the 0.55 NA optic, and (3) does the multi-patterning savings on 2–3 layers justify a $380M+ tool cost versus a 0.33-NA fleet expansion.
Who Has Bought, Who Has Deferred, and Why
Intel is the only chipmaker to publicly commit a High-NA HVM node: 14A risk production targeted for 2027 and volume production targeted for 2028, with EXE:5200B tools feeding Panther Lake (Core Ultra Series 3) on selected layers ahead of that node [S3][S4]. TSMC has stated it will skip High-NA for A14 and A16, extending 0.33-NA EUV with multi-patterning, while Samsung has not finalized a High-NA timeline and may defer to a Hyper-NA generation expected around 2030 [S2][S3]. SK Hynix and Micron are named as memory adopters evaluating High-NA for stacked-DRAM overlay budgets, but no firm HVM dates are public.
By September 8, 2026, Intel and ASML jointly disclosed that more than 1,000,000 300 mm wafers had passed through High-NA EXE-series scanners, a cumulative tally covering installation and certification, R&D, and volume manufacturing on select Panther Lake layers, announced at the SPIE Photomask Technology + Extreme Ultraviolet Lithography conference [S4]. The breakdown matters: a meaningful share of those wafers are running production silicon, not just test wafers, which is why Intel shares moved up roughly 5% and ASML shares about 4% on the news cycle [S4]. The wafer milestone reframes the foundry race: Intel is no longer running R&D-only High-NA; it is the only operator with a multi-hundred-thousand-wafer production data set, and TSMC's cost-driven delay now carries a competitive-data lag. For background on how lithography choices tie back to broader fab equipment allocation, the Digital Thread vs Digital Twin in Manufacturing framing is useful when mapping High-NA tool data into process control loops.
Memory Fab EUV Pull and the 3D DRAM Overlay Question
Memory manufacturers were historically EUV-light, often running one to two EUV layers per wafer on the most critical DRAM patterning steps, but the intensity is rising as Samsung, SK Hynix, and Micron push 1z, 1α, and 1β DRAM nodes [S1]. 3D DRAM, where cell arrays stack vertically rather than scale laterally, adds overlay and alignment budgets that pull memory fabs into the same High-NA allocation queue as logic foundries, and that compounded pull is a key reason ASML's installed base management line is growing 25% per year while systems bookings set records [S1].
The practical effect on equipment allocation: memory fabs are now competing for EUV slots that historically went to TSMC, Samsung Foundry, and Intel Foundry, and that shifts delivery prioritization logic for ASML's order management team through 2026 and 2027. The pattern is similar to what process engineers see when Steel Strapping Sizes 12.7–31.75 mm demand forces a single steel-mill allocation queue across packaging and construction buyers: total capacity is fixed, and the new entrant (memory) pushes the legacy buyer (logic) toward longer lead times.
Standards, Sourcing, and What the Numbers Will Look Like in 2027
No new EUV-specific ISO or IEC standard has been published in the research material to pin High-NA acceptance criteria to, so the relevant gates remain fab-internal: overlay budget per critical layer, mask blank defectivity for 0.55 NA, and resist performance at 8 nm single-exposure resolution. Industry sourcing in the research traces to ASML's own September 2026 disclosure on installed base, to SPIE Photomask 2026 conference coverage, and to ASML Q1 2026 earnings and CFO commentary on the 60+ Low-NA and roughly 10 High-NA shipment plan [S1][S4][S6].
The trackable signals through 2027 are concrete: ASML's full-year 2026 EUV shipment total (Low-NA plus High-NA), Intel's 14A risk-production wafer count in 2027, and any public TSMC statement on whether A14 stays on 0.33-NA multi-patterning or pivots to High-NA. If the 1 million High-NA wafer figure at Intel scales to a 5–10 million run-rate by end of 2027, the industry conversation shifts from "is High-NA real" to "what is the marginal wafer cost versus multi-patterning at A10 and beyond." On adjacent fab tooling, the Digital FMEA Linked to Control Plans approach will be where the High-NA stitching-risk FMEA lands for any 14A-tier process team, and a laser-distance-meter spec reference is a useful proxy for the overlay metrology stack around a High-NA tool.
For component-level specifications, see high voltage tester, and checking and testing apparatus.