TSMC's CoWoS-S and CoWoS-L lines are reported fully booked for 2026, with monthly output scaling from 75–80k WPM in late 2025 toward a 120–130k WPM exit run-rate by December 2026, against an aggregate customer demand approaching 1.0 million wafers [S1][S2]. NVIDIA alone is estimated to absorb roughly 595,000 wafers, about 60% of the 2026 pool, with CoWoS-L commanding an estimated 70% of that allocation as Blackwell B100/B200 and the Rubin generation shift off the legacy silicon interposer [S1][S6].
The 2024-to-2026 demand curve is steep: roughly 370,000 wafers in 2024, ~670,000 in 2025, and ~1.0 million in 2026 per allocation trackers, while capacity has grown from 35–40k WPM to a targeted 120–130k WPM over the same window [S1][S5]. The ratio that matters to a process engineer is not wafer-per-month but booking density: TSMC's July 16, 2026 earnings call framed the situation as "packaging capacity is so tight that now it's limiting my customers' growth" [S1].
CoWoS-S vs CoWoS-L: technical split and where each is used
CoWoS-S is the original 2.5D flow with a single monolithic silicon interposer, capped at about 3.3x reticle size (around 2,380 mm²) before cost and warpage break the geometry; AWS Trainium 2/3, Google's TPU v6/v7, and a long tail of HPC and networking ASICs still ride this variant [S3][S4]. CoWoS-L replaces the single-piece interposer with local silicon bridges embedded in an organic carrier, scaling today to about 5.5x reticle size (≈4,720 mm²), with TSMC's roadmap pointing to 9.5x (≈8,150 mm²) in 2027 and 14x (≈12,000 mm²) by 2029, which is what lets Blackwell and Rubin place more HBM stacks and larger compute dies side by side [S4].
Where the engineer cares about the spec: CoWoS-L is the variant carrying the largest AI packages in production, and within the 2026 mix roughly 70% of NVIDIA's allocation is on CoWoS-L, with the remaining 30% still on CoWoS-S for transitional SKUs and merchant parts [S1][S4][S6]. The capacity math is asymmetric, because a CoWoS-L wafer typically carries fewer but higher-value packages than a CoWoS-S wafer, and OSAT outsourcing ratios differ by variant, which is why capacity trackers quote wafer counts rather than package counts.
2026 capacity allocation: who gets what
The 2026 customer split is heavily concentrated at the top. NVIDIA is reported at roughly 60% (~595,000 wafers), Broadcom at about 15% (largely Google TPU, Meta MTIA, and custom ASICs), and AMD at a further slice targeting MI400/MI450 on CoWoS-L; the top three together account for an estimated 85%+ of 2026 wafer allocation [S1][S6]. Google's own 2026 demand has been quoted at ~240,000 wafers across TPU v7 (CoWoS-S) and limited TPU v8 (CoWoS-L, ~10% of volume), though TSMC's effective delivery to Google is estimated at 150,000–180,000 wafers against a ~6 million TPU-unit target, illustrating how allocation shortfalls propagate downstream [S2].
Industry-wide CoWoS capacity is expected to land at roughly 200k WPM by end-2026, with TSMC contributing ~120k WPM and OSAT partners (Amkor, ASE, SPIL) absorbing the remaining ~80k WPM as overflow [S4]. The Morgan Stanley supply-chain forecast cited in mid-2026 puts global customer-side CoWoS wafer demand at 1.384 million in 2026, rising to 2.682 million in 2027, an effective doubling that keeps the 2027 book open even as 2026 lines stay full [S3].
TSMC's 2026 outsourcing: who handles the overflow
TSMC plans to outsource an estimated 240,000–270,000 wafers of CoWoS work in 2026, with Amkor taking 180,000–190,000 wafers and SPIL handling 60,000–80,000 wafers; the split is driven by gross-margin rules (in-house work must clear 50% GM) and by TSMC's choice to free up AP7/AP8 for higher-complexity CoWoS-L flows [S2]. Amkor is already NVIDIA-qualified, which is the practical gating condition, and Google is reported to route roughly 95% of its outsourced CoWoS-S through the TSMC–Amkor pair [S2].
Margin ladders explain the routing: substrate-only OS work runs 35–40% gross margin, full CoW plus OS sits at 40–45% (with B200 packaging reportedly in the $300–400/unit band), and CoWoS-R (RDL interposer) can reach 50% [S2]. The OSAT lead-time of 26–39 weeks is materially shorter than the 52–78 weeks reported on TSMC's own CoWoS lines, which is why overflow economics, not just capacity, is part of the 2026 procurement plan [S1][S2]. For plant-side teams scoping industrial valve or flow meter lead-times, the parallel is familiar: the binding constraint rarely sits on the headline line.
Alternatives outside CoWoS: EMIB, I-Cube, and the second-source question
Intel's EMIB is the only flow with named external production today: AWS and Cisco are shipping silicon on EMIB, SpaceX and Tesla signed on around Intel's Q1 2026 Terafab call, and Google's TPU v8e is reported to land on EMIB in 2H 2027; Intel's external advanced-packaging outlook has moved from a few hundred million to north of a billion dollars across two earnings calls [S4]. Samsung I-Cube and X-Cube remain a third source, and ASE VIPack and Absolics round out the 2.5D/2D landscape for non-leading-edge workloads [S4][S5].
On a like-for-like spec comparison, CoWoS-S, CoWoS-L, and Intel EMIB solve the same interconnect problem with different geometry, which is the second-source question every hyperscaler procurement team is now mapping. The decision matrix looks like this for an AI accelerator procurement engineer evaluating 2026–2027 options: (1) Maximum die area: CoWoS-L 5.5x reticle today, 9.5x planned 2027, EMIB scales by stitching bridges, I-Cube tracks CoWoS-S class area. (2) Lead-time: CoWoS lines reported at 52–78 weeks, OSAT overflow at 26–39 weeks, EMIB at Intel-internal plus foundry partner capacity. (3) Supply security: CoWoS-L = single-source at TSMC, EMIB = single-source at Intel, I-Cube = single-source at Samsung, so a true second-source strategy still requires two of three flows qualified. (4) Customer concentration: CoWoS-L is functionally NVIDIA-locked for 2026; EMIB is the cleanest path for non-NVIDIA hyperscalers. For non-AI packaging, the same logic is visible in mature flow comparisons like PTFE vs Compressed Fiber Sealing Washers, where the second-source matrix matters more than the headline spec.
What the 2026 numbers do not solve
Capacity is being added fast, yet the booking window has not loosened: even at 120–130k WPM and 200k WPM industry-wide, demand of ~1.0–1.4 million wafers still outruns supply, and the 2027 doubling puts CoWoS-L on the critical path for every AI accelerator program launched after Rubin [S1][S3]. HBM allocation is the second binding axis, since CoWoS-L without HBM4/HBM4E stacks is just an empty interposer, and the 2nm wafer lead-time of 78–156 weeks (reported, not TSMC-confirmed) is the third axis that constrains the front-end [S1].
For 2026, the trackable signals are: (a) TSMC's quarterly CoWoS-L wafer disclosures on the October 2026 earnings call, (b) any movement on the NVIDIA-allocation share from ~60% as AMD MI400/MI450 and Google TPU v8 ramp, and (c) Intel EMIB revenue crossing the $1B external-packaging mark that CFO Zinsner flagged on CNBC; the thermal side of this packaging squeeze is also worth watching, since direct-to-chip cold-plate demand tracks the same AI-server build cycle, as covered in Direct-to-Chip Cold Plate Market 2026: Three Forecasts, One Thermal Bottleneck.
Spec-level background on the components involved: pressure transmitter.