ASML plans 65 low-NA EUV (TWINSCAN NXE) system shipments in 2026, climbing to 80-85 units in 2027, with the High-NA EXE:5200B at ~$380M per system already sold out through 2027 and 10 production systems live at 4 customers plus 3 more shipping as of Semicon Taiwan 2026 [S2][S3].
New EUV scanner lead times run 12-18 months from order to installation, versus 3-6 months for a qualified refurbished system, which makes allocation and cycle-time forecasting the binding constraint for sub-7nm fab ramps [S4].
Low-NA EUV (NXE:3800E) and High-NA EUV (EXE:5200B) Side by Side
The low-NA TWINSCAN NXE:3800E runs at 0.33 NA, 13.5 nm wavelength, 220 wafers per hour throughput, and ~$180M per system, patterning 7nm down to 2nm logic and is the only high-volume EUV platform shipping today [S2]. The High-NA TWINSCAN EXE:5200B uses 0.55 NA anamorphic optics, hits 135 wafers per hour in acceptance testing, lists at ~$380M ($350-400M installed), and is the first tool capable of sub-2nm single-exposure patterning with features up to 66% smaller than low-NA at the same pitch [S1][S3].
Throughput delta is the dominant trade-off: NXE:3800E delivers 220 WPH at ~$0.82M per WPH capex, while EXE:5200B lands near 135 WPH at ~$2.81M per WPH, a 3.4x capital intensity ratio that pushes High-NA into the layers where the resolution win is unavoidable, not blanket deployment across every critical layer [S2][S3]. The High-NA roadmap targets 160 WPH on EXE:5200C, 175 on EXE:5200D, 180 on EXE:5400E, and over 250 on the planned EXE:5600, closing the per-wafer cost gap over the next three generations [S3].
Who the Backlog Actually Serves
Intel operates the first production-graded High-NA system, EXE:5200B at D1X Oregon, and on July 15, 2026 select layers of Panther Lake (18A) chips became the first High-NA-patterned product to reach high-volume manufacturing, with Intel 14A risk production slated for 2027 [S3][S5].
Samsung took delivery of its first EXE:5200B in late 2025 with a second unit expected in H1 2026, and on September 8, 2026 committed to High-NA DRAM high-volume manufacturing in 2028, an industry first for memory [S1][S3]. SK hynix installed its EXE:5200B in September 2025 and set the same 2028 DRAM date, while Micron ordered tools without disclosing a production date [S1][S3]. imec received the EXE:52000 system in March 2026 (one of fewer than a dozen worldwide) and is targeting full qualification by Q4 2026 inside the EU-funded NanoIC pilot line [S1].
TSMC stated on September 8, 2026 that it intends to use High-NA in high-volume manufacturing from 2030, starting on 6-inch masks, and joined ASML in an industry initiative for 12-inch High-NA photomasks (pilot line 2031, production 2033), making it the only top-tier foundry publicly deferring High-NA past 2028 [S3].
Lead-Time Mechanics and the Refurbished Escape Valve
New EUV systems ship in 12-18 month cycles, while new ArF immersion tools run 9-15 months, ArF dry 6-12 months, KrF 4-8 months, and i-line 2-6 months, a stack that determines whether a 2027 capacity target is realistic on the day the order is signed [S4].
Refurbished EUV typically trades at 30-60% of new list pricing, with a 2019-vintage immersion scanner commonly landing in the $25M-$60M band versus $200M-$400M for new EUV, but the unit shipped is a single low-NA system and does not unlock any sub-2nm layer that requires High-NA [S4]. ASML systems hold resale value best because the installed base and service network are the deepest, which is why a used ASML PAS 5500/250 KrF at 110 nm resolution and 20 nm overlay is the lowest-risk refurbished pick for mature nodes [S4].
The five inspection points that decide whether a used tool is a bargain or a write-off are the optical column (lens contamination, illumination uniformity, laser power versus factory acceptance data), the wafer stage (positioning accuracy, encoder and interferometer condition, stiction at low velocity), complete historical maintenance records, light-source hours and pulses, and software/license entitlement transferability, none of which can be skipped without buying a future downtime line item [S4].
Pricing Stack and Cost-per-Wafer Implications
New EUV systems price in the $200M-$400M band, with the production NXE:3800E near $180M and the EXE:5200B near $380M, and the small set of global suppliers running multi-quarter lead times so procurement strategy now drives fab schedules as much as process engineering does [S2][S3][S4].
At fleet scale, 48 low-NA EUV systems were recognized in 2025 revenue for €11.6B (+39% year over year), giving an effective average system price around €242M including options, installation, and service kits, and 279 DUV systems contributed €12.0B in the same year [S2]. High-NA fleet availability stood at 84% in July 2026 with a 90% Q4 2026 target, meaning a 16% downtime drag today that fab planners have to model directly into wafer-out forecasts [S3].
The capex-per-wafer math flips between systems: at 135 WPH and ~$380M, EXE:5200B carries roughly $2.81M of tool capex per wafer of nameplate output, versus $0.82M for the NXE:3800E, and any throughput gain on EXE:5200C (160 WPH target) drops that ratio to about $2.38M per wafer without changing the tool price [S2][S3].
2026 vs 2027 Allocation Outlook
2026 EUV system shipments split roughly 65 low-NA plus a small High-NA increment (10 live, 3 shipping at Semicon Taiwan 2026, with imec's Q4 2026 qualification adding at least one more), and 2027 rises to 80-85 low-NA systems alongside the High-NA ramp into Intel 14A risk production [S2][S3].
ASML CEO Christophe Fouquet said the AI boom is not over and that memory makers are more aggressive on High-NA as low-NA EUV tools are all but sold out through 2027, which is the binding signal for any foundry still negotiating 2027-2028 capacity [S3]. The decision for new fabs is binary on the High-NA axis: order now for a 2027-2028 risk-production slot, wait until EXE:5200C and EXE:5200D throughput gains (160-175 WPH) lower cost per wafer, or qualify on low-NA and accept multi-patterning EUV at the 2nm and A14 nodes, which most leading-edge fabs are no longer willing to do [S3].
What to Track Before the Next Decision Point
First watch item: imec's EXE:5200 qualification at Q4 2026, since full qualification at the NanoIC pilot line is the gating event before any independent sub-2nm process data flows back to ASML's roadmap [S1]. Second watch item: whether Samsung and SK hynix convert their 2028 DRAM commitments into specific layer insertions and tool order additions before TSMC's 2030 high-volume date becomes the de facto industry schedule [S3].
Third watch item: fleet availability crossing the 90% Q4 2026 target, because every percentage point below 90% directly cuts effective wafer output on the installed High-NA base and forces customers to either order more EXE systems or accept slower ramp curves at Intel 14A and 18A follow-on nodes [S3].
For a parallel decision tree on capex-heavy single-tool bottlenecks with multi-quarter lead times, the per-sample cost framework applied to capital instrumentation uses the same utilization-and-throughput logic, and the aeroderivative vs heavy-duty gas turbine cost-per-kW comparison applies the same $/unit-output lens to a different capital class. Material-handling teams that need precise inventory counts around EUV-equipment receiving lanes can benchmark throughput in the VLM vs manual shelving accuracy study.
Spec-level background on the components involved: 3d scanner, industrial barcode scanner, and structured light scanner.