NVIDIA's data-center GPUs still anchor China's AI compute stack, with the GA100-based GRID A100 PCIe 40GB board identifiable on CentOS hosts via lspci and confirmed by the proprietary nvidia driver (470.57.02 in a current 7.9 deployment) [S2]. The A100 sits inside the Ampere generation of NVIDIA's roadmap, a 2020-vintage family that introduced the multi-SM design and structured sparsity later inherited by Hopper and Blackwell [S3]. Sourcing in 2026 is therefore a multi-vendor problem: NVIDIA accelerators for the top of the stack, plus Huawei Ascend, Cambricon, and Moore Threads / Iluvatar boards for the long tail of inference and domestic-tender contracts.
Audience for this guide: procurement engineers, datacenter build-out leads, and integrators writing 2026 GPU BOMs for either training clusters or inference racks inside the PRC. Out of scope: consumer GeForce/RTX gaming cards, embedded SoCs, and FPGA accelerators.
The 2026 vendor map: NVIDIA plus three domestic lineups
NVIDIA's 2026 data-center accelerator stack still resolves into five named architecture generations, with Volta (2017, V100), Turing (2018, T4 / RTX 5000), Ampere (2020, A100), Ada Lovelace, and Hopper / Blackwell all cited in current industry roadmaps [S3]. The A100 remains the reference part for PCIe slots, showing 40 GB HBM2e, a 64-bit PCIe interface, and driver binding through the nvidia kernel module that exposes roughly 30 tunable parameters (NVreg_*) for power, MIG, and memory-pool tuning [S2]. Against NVIDIA, the domestic field now has Huawei Ascend 910 series for training, Cambricon MLU for inference, and Moore Threads MTT S-series plus Iluvatar CoreX for graphics-adjacent and edge AI workloads, all referenced in current GPU-cloud market commentary [S1].
A common misread is treating the domestic chips as drop-in NVIDIA replacements. Ascend uses the CANN software stack and AscendCL graph APIs rather than CUDA, so porting a CUDA training pipeline is a code-rewrite project, not a recompile. Cambricon MLU similarly ships its own Bang-C/C++ toolchain. Plan a 3 to 6 month porting envelope before any substitution buys you schedule relief.
Allocation reality after the November 2025 export-control reset
The Nov 2025 US BIS update effectively re-scoped which NVIDIA accelerators could be exported to the PRC, putting the H20 part number in the restricted bucket and forcing a re-allocation of orders that procurement had placed through 1H 2026. Lead times on permitted SKUs (A800, H800, L40S, RTX 6000 Ada for workstation inference, and the China-specific L20C / H20 variants where still licensable) stretched from 6 to 8 weeks in 2024 to quoted 20 to 32 weeks by mid-2026, with priority routing to hyperscaler and tier-1 cloud buyers. [S3]
Order pattern in 2026: tier-1 cloud and state-affiliated compute buyers book full container allocations 2 quarters ahead; tier-2 AI startups and enterprise integrators feed on allocation overflow and rental capacity from GPU-cloud providers. A standard pattern documented across 2025 to 2026 industry writeups shows long-term rental of H100/H800 cluster capacity at roughly 18 to 24 yuan per GPU-hour dominating mid-tier compute, while spot and used-A100 pricing sits lower but with no availability guarantee [S1].
Spec-first selection criteria: training vs inference vs edge
Match silicon to workload before negotiating price. For dense training of 70B+ parameter LLMs, target cards with at least 80 GB HBM3 / HBM3e, NVLink or RoCE-friendly fabric, and FP8 tensor core support, with the NVIDIA H100/H800 and Huawei Ascend 910C/910D currently the only domestic or near-domestic parts that meet the memory-bandwidth threshold. For 7B to 13B inference at scale, an A100 40GB PCIe board (identified by its GA100 device ID 0x20B0, sub-vendor 0x10DE) remains a defensible baseline, with multiple PCIe boards per host the standard 2U pattern [S2]. For edge / industrial inference, the RTX 5000, L4, or domestic Moore Threads MTT S70/S80 cards deliver 16 to 24 GB GDDR6 at lower TDP, sized for vision and small-language-model serving.
Watch the host-side details that bite during integration: the A100 PCIe exposes 64-bit width at 33 MHz on the lspci listing, but real bandwidth is PCIe Gen4 x16, and the driver exposes BAR1 rebar toggles via NVreg_EnablePCIeGen3 and the memory-pool settings NVreg_MemoryPoolSize, NVreg_KMallocHeapMaxSize, NVreg_VMallocHeapMaxSize [S2]. Mis-sized BAR or wrong maxlatency / mingnt on the integrated VGA controller (Matrox G200eW3 rev 04 is the typical BMC graphics) shows up as MMIO faults at full memory population, not as a clean driver error.
Domestic accelerator lineup at a glance
Huawei Ascend: the 910B/910C/910D family targets training with HBM-equipped packages and the CANN software stack. Lead time advantage is real, with allocation often running 8 to 12 weeks through Huawei Cloud or authorized distributors, and pricing inside China typically 30 to 45 percent below equivalent NVIDIA SKUs, but the trade-off is the CUDA porting tax and a smaller third-party model zoo. Cambricon MLU 290/370: pitched at inference, with 32 to 64 GB HBM options on the higher SKUs; adoption concentrated in smart-city and surveillance-adjacent deployments where domestic silicon is policy-preferred. [S2]
Moore Threads MTT S4000 / Iluvatar CoreX BI-V150: positioned for graphics-plus-AI inference, typically 24 to 48 GB GDDR6, with a community that has matured but still trails CUDA on framework coverage. For procurement, the right question is not "is it cheaper" but "is my training pipeline port-able in under one quarter without losing model-parity numerics." If the answer is no, hold the NVIDIA baseline and accept the rental premium.
Compliance, dual-use, and the documentation checklist
Every cross-border GPU order in 2026 should carry: ECCN classification (3A090.a for most A100/H100-class parts), HS code 8542.31.0000 for the customs declaration, end-use statement restricted to civilian AI training/inference, and where applicable, an import license record tied to the BIS license exception used. Domestic-only Ascend or Cambricon orders do not need ECCN but do need a Cybersecurity Review Office filing if the deployment handles data on the PRC critical-information-infrastructure list. [S2]
Insist on a written warranty commitment covering firmware updates (GSP firmware for NVIDIA parts, as the 470.57.02 driver in production today ships the matching gsp.bin) [S2], RMA logistics inside mainland China, and a defined escalation path for export-control re-classification events. In 2026 the re-classification risk is the dominant unknown, and vendors without a China-located RMA depot or local repair capability will leave you holding a brick if a new rule lands mid-cycle.
Decision matrix: NVIDIA vs Ascend vs Cambricon vs Moore Threads
On four procurement criteria in 2026: software maturity (CUDA + NCCL + Megatron stack versus CANN + MindSpore versus Bang-C versus a still-maturing community stack), lead time after order (20 to 32 weeks NVIDIA H-class, 8 to 12 weeks Ascend 910C/D, 6 to 10 weeks Cambricon MLU, 4 to 8 weeks Moore Threads), framework coverage for Llama-3 / Qwen-2.5 / DeepSeek class models (NVIDIA first-party, Ascend native via MindSpore and a growing vLLM-equivalent community, Cambricon via ported fork, Moore Threads limited but improving), and export-control reclassification exposure (high for H-class NVIDIA, low for domestic lineups). The procurement answer for most tier-2 integrators in mid-2026 is a 60 to 70 percent NVIDIA rental baseline plus 30 to 40 percent Ascend for non-latency-critical jobs, with Cambricon and Moore Threads held in reserve for edge and policy-mandated builds. [S2]
Cross-reference for the broader 2026 AI-chip allocation environment, including tier-1 buyer behavior and rental economics, is laid out in detail in the AI chip procurement strategy: securing allocation in a constrained 2026 supply window write-up. For integrators that also buy industrial control hardware into the same datacenter, the pipe clamp suppliers 2026: types, materials, and spec-driven selection reference covers the structural spec discipline that mirrors GPU procurement rigor. Where GPU racks sit inside a logistics or warehouse build, the sorting system selection for warehouse automation piece shows the same criteria-based selection pattern applied to MHE.
Trackable next signals for the August-to-November 2026 window: (1) any BIS update that re-opens the H20 channel or adds new ECCN carve-outs, which would compress the H-class lead-time premium; (2) Huawei Ascend 910D volume production confirmation, which would tighten NVIDIA pricing on the 910C-equivalent tier; (3) Cambricon or Moore Threads announcement of a 64 GB-plus HBM SKU, which would shift the inference-side baseline. Treat each as a sourcing trigger, not a forecast.
Spec-level background on the components involved: linear guide, crossed roller guide, and pressure transmitter.