HBM4 was published as a JEDEC standard in April 2025, doubling the per-stack channel count to 32×64-bit and raising the per-stack ceiling to 64 GB and 2048 GB/s versus 48 GB and 1229 GB/s for HBM3E [S1].
SK Hynix, Samsung, and Micron are the three qualified HBM manufacturers in 2025, with TSMC producing the base die and CoWoS interposers that physically host the stack adjacent to the accelerator [S1][S2]. The combination of TSVs, micro-bump pitch, and die thinning makes HBM the highest-cost DRAM node in production, and the manufacturing flow now runs an early wafer-level test step to gate known-good-die yield before expensive 2.5D assembly [S7].
JEDEC HBM standard lineage and the 2025-2026 spec delta
JEDEC standard dates anchor every HBM contract: HBM1 in October 2013, HBM2 in January 2016, HBM2E in August 2019, HBM3 in January 2022, HBM3E in May 2023, and HBM4 in April 2025 [S1]. Per-pin data rate climbed from 1.0 Gb/s (HBM1) to 9.8 Gb/s (HBM3E), then reset to 8 Gb/s in HBM4 because the spec doubles the channel count rather than pushing signaling rate further [S1].
Bus width is the structural reason HBM wins on bandwidth: HBM3 delivers a 1024-bit memory bus per stack versus 32-bit per chip for GDDR6X and 64-bit for DDR5, so HBM holds an order-of-magnitude bandwidth advantage per package even at lower per-pin rates [S5]. That wider bus is the single largest manufacturing stress: a HBM3E stack has over 1000 wires running between the stack and the adjacent XPU, which is not routable on a PCB or package substrate and forces silicon/organic interposer assembly via TSMC CoWoS [S2].
Why HBM yield, not density, is the gating constraint
Manufacturing complexity in HBM is dominated by the 3D stack and TSV connection sophistication, not by the DRAM cell shrink itself, and that is the structural reason cost runs well above planar DDR5 [S5]. Applied Materials identifies four process steps where defects propagate into yield loss: through-silicon via (TSV) formation, micro-bump pillar deposition, thin-die stacking, and the base-die interconnect [S3]. Higher-aspect-ratio TSVs need low-temperature dielectric liners with uniform sidewall coverage, and Applied's Producer InVia 2 CVD plus Endura Ventura 2 PVD are positioned as the dielectric and barrier-seed deposition reference for this step [S3].
Micro-bump pitch is the second yield lever. As bump and bond-pad dimensions shrink, contact resistance grows exponentially; under-bump metallization (UBM) PVD and ECD preclean, for example Applied's Volaris preclean paired with Nokota ECD, set the contact-resistance budget for each stack tier [S3]. Thin-die warpage is the third lever: a back-side PECVD film on the wafer (Applied's Producer Avila) is used to modulate compressive/tensile stress so a 30-50 µm thinned die stays flat enough for hybrid bonding at 12-Hi and 16-Hi [S3]. These are not optional steps, they are the difference between a shippable HBM3E part and a stack that fails final test.
Test-shift left: why wafer-level probe now matters more than final
Industry guidance as of May 2026 is to move HBM test earlier in the flow, with wafer-level test (WLT) before stacking the TSV and 2.5D assembly, because the cost of finding a bad die after it is bonded into a 12-Hi stack and packaged on CoWoS is several times the cost of finding it at probe [S7]. The economic case rests on a 3-to-1 wafer capacity ratio between HBM and DDR5 that Micron has cited: every HBM wafer ramp directly compresses commodity DRAM supply, so yield loss at the back end is multiplied by the displacement cost on the DDR5 line [S1].
Test coverage at WLT has to include DC parametric, speed binning, and partial array test, because HBM stacks cannot be fully exercised for bandwidth until they are mounted on a logic die. Speed binning at wafer is therefore a forecast, not a guarantee, and final test on the packaged part is still required for the JEDEC per-pin data rate and the 1024-bit (HBM3) or 2048-bit (HBM4) bus width contract [S1][S5][S7]. For procurement, this means accepting that a known-good-die (KGD) certificate is necessary but not sufficient; the contract should also call out final-test yield data and post-packaging repair rate.
Supply concentration and base-die risk
Three suppliers, SK Hynix, Samsung, and Micron, hold essentially all qualified HBM capacity in 2025-2026, and TSMC is the foundry for the HBM base die as well as the CoWoS interposer that hosts the stack [S1]. That stack creates a single point of failure at the packaging step: any CoWoS capacity constraint or base-die yield problem at TSMC immediately throttles the HBM3E/HBM4 output of all three memory vendors, regardless of their own fab utilization [S1][S2].
Commodity DRAM capacity is being displaced by HBM at roughly the 3-to-1 wafer ratio Micron disclosed, and standard DRAM pricing has seen compounded increases exceeding 200% from early 2025 into early 2026 as a result [S1]. For an industrial or AI-accelerator buyer, the practical reading is that HBM lead time is now packaging-bound, not wafer-bound, and qualified-vendor qualification audits should specifically cover the base-die supply chain, not just the memory fab.
Selection criteria for buyers and process engineers
Compare the live HBM options against four criteria before signing a spec: per-pin data rate (signal integrity budget), stack height and capacity per stack, base-die and packaging dependency, and KGD-plus-final-test yield disclosure. On per-pin rate, HBM3E at 9.8 Gb/s beats HBM4 at 8 Gb/s, but HBM4 wins on per-stack bandwidth (2048 vs 1229 GB/s) because of the wider 32×64-bit interface [S1]. On stack height, 8-Hi HBM3E is the volume baseline, 12-Hi HBM3E is in ramp, and 16-Hi HBM4 is the 2026-2027 target [S1][S2]. On packaging, every HBM3E/HBM4 part is gated by TSMC CoWoS regardless of memory vendor [S1][S2]. On test, demand wafer-level probe data plus post-stack known-good-die and final-test yield in writing [S7].
For industrial and process-control platforms, the HBM standard itself is not the procurement target. A buyer specifying HBM is really specifying an AI accelerator or a high-bandwidth data-acquisition card, and the relevant selection criteria sit on the host side, including the flow meter, pressure transmitter, and power quality analyzer signal chains feeding the accelerator. HBM quality and standards are upstream inputs to that host system, not a directly-specified commodity for most process plants, so the right engagement is with the accelerator OEM on KGD and final-test documentation rather than a direct HBM vendor contract.
Track two signals over the next two quarters: (1) the HBM4E or HBM4 refresh revision that JEDEC is expected to publish, which will set the next per-pin rate target beyond the current 8 Gb/s [S1]; (2) any disclosure of base-die yield or CoWoS allocation from TSMC, since that is the structural bottleneck for all three HBM vendors and the single most predictive indicator of HBM supply into 2027 [S1][S2].
See also our earlier report, Steel Rebar Manufacturing Equipment: A 2026 Spec and Selection Guide.