TrendForce projects HBM contract prices will surge multiples higher in 2027 as HBM4 becomes the mainstream generation and wafer allocation tightens, with HBM wafer input rising to roughly 18%, 22%, and 30% of total DRAM wafer input across the top three suppliers by year-end 2025, 2026, and 2027 respectively [S2].
DataNext Research sizes the global HBM market at USD 35B in 2025, USD 46B in 2026, and USD 205B by 2036 (16.1% CAGR), with SK hynix holding above 60% share in a three-supplier oligopoly alongside Micron and Samsung, and HBM capacity reported as sold out well in advance of delivery [S5].
HBM4 ramps 2026: Rubin, MI400, and 288-384GB per accelerator
HBM4 enters volume with 8 Gbps pin speed (HBM4e at 10 Gbps), 2048 I/Os widening to 4096, 2.0-2.5 TB/s per stack, and 12/16-Hi stacks delivering 36-48 GB per stack (HBM4e 48-64 GB) at 75-80 W [S3]. NVIDIA Rubin integrates 8 HBM4 sites for 288-384 GB at 16-32 TB/s of aggregate bandwidth, while AMD MI400 carries 432 GB at 19.6 TB/s, both using microbump MR-MUF packaging and direct-to-chip liquid cooling [S3].
Per-chip HBM capacity is jumping from 96-192 GB on 2025 accelerators to 216-288 GB on 2026 AI ASICs, then 384 GB on Rubin Ultra in 2027, a roughly 2x lift in two years that directly drives bit demand [S2]. This compares to current HBM3e 8-Hi stacks at 24 GB per stack and roughly 1.2 TB/s per stack, with the H200 reaching 141 GB across 6 stacks and the B200 reaching 192 GB [S4]. For context, the H100 SXM with 80 GB HBM3 and 3.35 TB/s bandwidth serves as the baseline for today's 70B-class model deployments at a street price of USD 25,000-30,000 [S4].
HBM5 to HBM8 roadmap: 4 TB/s to 64 TB/s per stack by 2038
The KAIST Memory Systems Laboratory and TERA Interconnection and Packaging joint briefing outlines five successive HBM generations, with HBM4 (2026), HBM5 (2029), HBM6 (2032), HBM7 (early 2030s), and HBM8 (2038) targeting multi-terabyte memory on 15,000 W accelerator platforms [S1]. HBM5 lifts bandwidth to 4.0 TB/s per stack with 4096 I/Os, 16-Hi 80 GB stacks at 100 W, and near-memory computing where the base die hosts GPU functions; NVIDIA Feynman integrates 8 HBM5 sites for 400-500 GB at a 4400 W TDP [S3].
HBM6 doubles again to 8.0 TB/s and 96-120 GB per stack at 120 W via 16/20-Hi stacks and bumpless Cu-Cu direct bonding on hybrid silicon+glass interposers, enabling 16-site configurations of 1536-1920 GB and 128-256 TB/s aggregate bandwidth [S3]. HBM7 reaches 24.0 TB/s with 160-192 GB stacks and introduces HBM-HBF (NAND-based High Bandwidth Flash at 1 TB/stack, 4096 GB/s interconnect), while HBM8 closes the roadmap at 32 Gbps, 16,384 I/Os, 64.0 TB/s per stack, and 200-240 GB per stack at 180 W [S1][S3]. Thermal management is the gating constraint: HBM5 dedicates roughly 30% of die area to thermal through-silicon vias, and HBM6 onward requires immersion cooling and backside power delivery [S3].
Supply, pricing power, and the conventional DRAM trade-off
HBM4 2027 contract negotiations are shifting the buyer-supplier balance in suppliers' favor because the annual pricing mechanism has lagged quarterly spot DRAM increases since 2H 2025, and per-wafer HBM revenue fell below DDR5 64 GB RDIMM in 1Q 2026 for the first time, giving suppliers cover to reallocate wafer starts [S2]. TrendForce projects HBM bit supply will reach roughly 8%, 9%, and 13% of total DRAM bit supply by year-end 2025, 2026, and 2027, intensifying the crowding-out effect on conventional DRAM as HBM die sizes grow with each generation [S2].
The supply ceiling is set not by wafer fabs but by advanced packaging: HBM depends on through-silicon vias and 2.5D integration such as TSMC's CoWoS, and DataNext highlights that glass interposer fabrication for HBM6 remains an open supply-chain challenge [S3][S5]. AI data center accelerators consume the large majority of HBM output, with NVIDIA H100 at 80 GB HBM3, H200 at 141 GB HBM3e, B200 at 192 GB HBM3e, and AMD MI300X at 192 GB HBM3 illustrating per-device attach rates that scale linearly with accelerator shipments [S5]. The broader AI memory ecosystem, including RDIMMs, server LPDDR, and edge DRAM, absorbs spillover demand as suppliers rebalance wafer allocation [S2].
Selection criteria: matching HBM generation to accelerator platform
For 2026-2027 procurement, the decision matrix is bandwidth-per-stack versus capacity-per-GPU versus thermal envelope. HBM3e remains the volume baseline for current inference fleets: 8-Hi 24 GB stacks at roughly 1.2 TB/s, with the H200 delivering 141 GB / 4.8 TB/s per GPU at USD 30,000-35,000 street (USD 213-248/GB) and the B200 at 192 GB / 8.0 TB/s [S4]. HBM4 is the right pick for new Rubin and MI400 builds needing 288-432 GB per accelerator and 16-19.6 TB/s, at the cost of microbump MR-MUF packaging and mandatory direct-to-chip liquid cooling [S3].
Engineers specifying HBM5+ (2029+) should plan for immersion cooling, hybrid interposers, and base-die compute integration rather than treating HBM as a passive component, with thermal through-silicon vias consuming 30% of die area on HBM5 and Cu-Cu bumpless bonding replacing microbump stacking from HBM6 onward [S3]. For comparison against current accelerators, the AMD MI300X delivers 192 GB HBM3 at 5.3 TB/s for USD 12,000-15,000 (USD 63-78/GB) and the MI325X lifts to 256 GB HBM3e at 6.0 TB/s, both well below NVIDIA HBM3e pricing per GB [S4]. Skipping to HBM6+ before 2032 is impractical because glass interposer supply is not yet scaled [S3].
Use cases, limitations, and the 2026 memory wall
Production AI serving is memory-constrained before it is compute-constrained: an 80 GB H100 can serve 40B-parameter models at FP16 or 80B at INT8, and the 141 GB H200 enables comfortable 70B-class serving with longer context windows, but 400B+ MoE models such as Llama 4 Maverick cannot fit a single H200 at full precision and require quantization or multi-GPU tensor parallelism [S4]. The B200's 192 GB and the projected B300's 288 GB (HBM3e 12-Hi) push single-GPU frontier-model serving closer to feasible, but model growth continues to outpace memory growth [S4].
For hyperscaler build-outs, the HBM constraint is the binding one, not raw compute, and the operational failure modes, including out-of-memory crashes during traffic spikes, KV-cache saturation, and context-window-driven VRAM bloat, all trace back to HBM capacity and bandwidth [S4]. For edge and inference-at-scale deployments, HBM7's HBM-LPDDR integration is the relevant 2030s milestone, pairing low-power memory with stacked HBM to support distributed inference topologies [S3]. Forecasts through 2028 remain gated by HBM3e and HBM4 capacity rather than by accelerator silicon, and 2030+ forecasts depend on TSV yield, CoWoS and glass interposer throughput, and immersion-cooling data-center retrofits [S1][S2][S5]. Tracking two signals will confirm the trajectory: the 2027 HBM4 contract pricing outcome [S2], and whether glass interposer and bumpless Cu-Cu bonding reach volume production for HBM6 in 2032 [S3].
Demand-side context for the broader advanced-packaging chain, where CoWoS and 2.5D throughput gate HBM deliveries, is detailed in Advanced Packaging Demand 2026-2030: Capacity, Forecasts, and Platform Breakdown; equipment-side exposure is covered in Chip Packaging Demand 2026-2030: Capacity, AI Driver, and Equipment Map; and the regional vendor map for packaging capacity sits in Chip Packaging Market Share: 2026 Vendor Map by Region and Technology.
Spec-level background on the components involved: pressure transmitter, flow meter, and industrial valve.