Capacity planning for a printed circuit board line begins with three Oracle-defined tiers — Resource Requirements Planning (RRP) for 12-month to 3-year horizons, Rough Cut Capacity Planning (RCCP) at critical work centers, and Capacity Requirements Planning (CRP) matched to MRP output [S2].
For PCB specifically, the practical translation is: forecast unit volume and layer count → map each process step (imaging, etching, plating, AOI, electrical test) to available hours → identify the bottleneck work center → either re-balance the line or add shifts, which mirrors the Oracle rule that if sufficient capacity is not available, you must alter the plan or the capacity [S2].
PCB Stack-Up Definitions That Drive the Capacity Model
A PCB stack-up confirmed in engineering release lists five mandatory layers — line layers, hole layers, solder mask, silkscreen/character, and outline — and any change to layer count or board thickness directly rewrites the capacity equation at imaging and lamination [S3].
For example, jumping from a 4-layer to an 8-layer board roughly doubles exposure and lamination cycle time, while adding blind/buried vias adds a second drilling cycle and an extra plating step. Process engineers treat these as discrete work-center events, not percentages, when feeding CRP [S3].
Selection Criteria: Which Capacity Tier Applies to PCB
RRP answers long-range questions such as whether to add a second laser-drill or expand the existing facility, and it operates at the product family level with a 12-month to 3-year planning horizon [S2]. RCCP isolates the critical work center — typically the direct imaging or the electroless copper line — where a single shift of capacity can gate the entire monthly output [S2].
CRP then matches available equipment hours and personnel to MRP-generated demand at the part-number level, and the planner's response is binary: revise the material plan or add a resource such as a skilled operator, a new AOI station, or additional floor space [S2]. For a detailed equipment-by-equipment walkthrough, the PCB manufacturing equipment selection guide maps imaging, etching, plating, and inspection to their typical bottleneck roles.
Comparison: RRP vs RCCP vs CRP for a 6-Layer Multilayer Job
Decision criteria used by PCB planners across the three Oracle tiers: planning horizon, data granularity, typical output, and the staffing/capital question it answers [S2].
On a 6-layer, 1.6 mm board with ENIG finish, RRP evaluates whether the next laser-drill is justified across the 12-month product family mix, RCCP flags whether the electroless copper line or the lamination press is the binding constraint this quarter, and CRP tells the shift supervisor whether tonight's lot can clear with current operators or requires pulling a third shift. The pattern holds across fabs: the longer the horizon, the coarser the data, and the more capital-intensive the question [S2].
Who This Framework Is For — and Where It Breaks
Capacity planning is for any PCB shop running 10 or more part numbers, where the monthly mix changes and a single bottleneck determines whether a quoted lead time is honest or aspirational. It is not for prototype-only fabs running 1-3 boards per build, where the bottleneck is engineering iteration, not work-center hours [S2].
It also breaks when engineering release does not lock the stack-up — every layer-count change after release invalidates the CRP run. Common failures include quoting 6-layer lead time on a 4-layer capacity model, skipping solder-mask imaging in the hour count, and treating ENIG as a single step when it is electroless nickel plus immersion gold plus three rinses. For a complementary view on how upstream substrate availability feeds the same planning problem, the PE resin shortage 2026 sourcing risk piece covers the raw-material side of the same planning chain.
Standards and Sourcing Anchors
The engineer-facing vocabulary that feeds capacity models — approval, sample, attached, previous version, the same as, tolerance, spec — is consistent across Chinese and English PCB release notes, which lets a planning team use the same MRP inputs across plants in different regions [S3].
Per Oracle's EnterpriseOne model, demand forecasting is the logical starting point for a resource requirements plan but is not the plan itself; the forecast feeds RRP, which then validates whether the company's strategic business plan is supportable by the actual work-center calendar [S2]. For silicon-driven fabs where the substrate side of the chain is also critical, the silicon wafer quality standards 2026 spec map provides the upstream quality anchor that pairs with this capacity view.
Limitations and Common Failure Modes
The Oracle model assumes work-center capacity can be expressed in available hours per time bucket, which is true for most PCB steps but misleads at laser-drilling and direct imaging, where the rate-limiting variable is feature count per panel, not clock time [S2].
Common failure modes: ignoring re-work loop time, treating yield loss as a constant when it varies with layer count, and booking AOI only at the end when in-line AOI after etch and after plating catches defects hours earlier and reduces WIP. The fix is to instrument each work center with actual cycle-time data, run RCCP monthly, and rerun CRP every time the stack-up or the panel utilization changes [S2]. For an adjacent cost-side lens on capital-intensive process lines, the flat belt total cost of ownership analysis applies the same lifecycle thinking to conveyor-driven lines that often feed PCB shops.
Trackable next signal: a 6-layer multilayer line at 80% RCCP utilization is the threshold where most PCB planners begin evaluating a second direct-imaging shift; if the forecast moves above that line for two consecutive RCCP cycles, the capex review is the trackable next node.
Spec-level background on the components involved: pressure transmitter, flow meter, and industrial valve.