The i-TOPCon process flow adds an ultra-thin tunnel-oxide (≈1–2 nm) layer plus a doped polycrystalline-silicon film on the rear of an n-type c-Si wafer, then runs high-temperature anneal, BBr3 diffusion, PECVD SiNx anti-reflection coating and metallization on a line that is largely retrofittable from PERC tooling [S2][S5].
On the cell, 18 silver busbars 20±5 mm wide are screen-printed on 210×210 mm wafers 130±13 µm thick, with silicon-nitride ARC and 16-busbar/18-busbar front-grid patterns common in volume production [S4]. On the module side, N-TOPCon glass-glass laminates in 2025 catalogue data span 420 W to 595 W with 21.5%–23.87% module efficiency under STC 1000 W/m², AM1.5, cell 25 °C [S3].
Wafer prep and rear-side tunnel-oxide deposition
Wafer prep starts with a KOH-based chemical texturing etch that removes ~5–10 µm of saw-damaged silicon from each side of the c-Si wafer, after which an RCA-style clean removes organics and metal residues [S5]. A BBr3 tube-furnace diffusion step then grows the p+ emitter on the front, and a single-side HF/HNO3 etch strips the parasitic emitter from the rear [S5].
The TOPCon signature layers are deposited on that cleaned rear: an ultra-thin tunnel oxide (~1–2 nm, SiO2 grown by wet-chemical or thermal means) followed by an in-situ doped n-type polycrystalline-silicon film via LPCVD, PECVD or PEALD variants [S2][S6]. The polysilicon thickness typically sits in the 100–200 nm band; the oxide is thin enough for quantum-mechanical tunnelling yet thick enough to block hole recombination [S2].
A high-temperature anneal (>900 °C, often a dopant-driving step shared with the front emitter) crystallises and activates the poly-Si, drives hydrogen toward the c-Si interface and conditions the contact for sub-1 fA/cm² saturation-current densities on the rear [S2][S6]. Process tool vendors deliberately co-integrate oxide growth, poly deposition and anneal into one cluster to keep the flow lean, in line with PV-Manufacturing's "lean process flow" guidance for i-TOPCon [S6].
Front-side emitter, ARC and metallization
After rear-side TOPCon stack deposition, the front p+ emitter is formed (BBr3 diffusion, ~900 °C) and passivated with a PECVD silicon-nitride anti-reflection coating 70–80 nm thick, tuned for refractive index n≈2.05 at 633 nm [S5]. Al2O3/SiNx stacks are sometimes added for further field-effect passivation; cell makers are increasingly substituting aluminium oxide for the rear SiNx on bifacial products.
Front-side metallization is silver-paste screen printing through 18-busbar grids, with finger width tightening toward 20±5 mm and busbar pitch shrinking to 16–18 busbar layouts for G12 wafers (210×210 mm) [S4]. A contact-firing step at ~750–820 °C peak fires the silver through the SiNx to the emitter, with the co-fire also driving the rear poly-Si doping to its final profile [S2][S6].
Industrial TOPCon cells in volume production now reach mass-production average efficiencies in the mid-25% range, and commercial TOPCon modules (e.g. 570–595 W glass-glass bifacial, 23.0%–23.87% module efficiency) are produced with ±3% STC power tolerance per the manufacturer's published ratings [S3]. The same datasheet shows bifacial gain allowing module power to scale with albedo, a key TOPCon selling point over monofacial PERC.
2025 Xi'an outdoor degradation evidence and CPIA 1 GW scenario
Industry field data from a 2023-11 to 2025-08 outdoor campaign at the Xi'an test field (extremes +41.8 °C to -20 °C, 500–750 mm/yr rainfall concentrated in summer/autumn, ~1500 sunshine hours/yr) compared 9 TOPCon, 4 BC and 4 HJT modules under matched electrical measurement at 5-second IV logging [S1]. Three TOPCon samples recorded first-year degradation between 0.52% and 1.48%, all under the industry's 1.5% first-year benchmark; two BC modules registered 2.27%–2.38%, and two HJT modules 4.02%–4.43% [S1].
BC split sharply: a 600 W unit held at 1.34% over 350 days, while a 455 W unit reached 3.67% by day 566, exceeding the limit; HJT remained >3% across re-tests, attributed by the test authors to low-temperature silver-paste degradation under prolonged heat-and-humidity exposure [S1].
The financial translation matters: per CPIA modelling cited in the same field report, a 1 GW plant whose annual degradation rises from 0.7% to 1.0% loses ~625 million kWh over 25 years, with revenue impact above 250 million RMB [S1]. The same report cites a 6–9 fen/W TOPCon-vs-BC price gap; on a 1 GW (DC) build that translates to 60–90 million RMB extra module cost for BC, and an LCOE gap of 0.015–0.02 RMB/kWh favouring TOPCon [S1].
Process options: LPCVD vs PECVD vs PEALD for the rear stack
The dominant deposition routes for the rear tunnel-oxide/poly-Si stack are LPCVD, PECVD and PEALD, each with different throughput, cost and wrap-around behaviour [S2][S6]. LPCVD gives the highest-quality poly-Si and best passivation but is a batch furnace tool with the highest capex per wafer; PECVD enables in-line single-side deposition with no HF wrap-around clean and lower tool cost; PEALD sits between them on throughput and enables ultra-thin SiO2 with sub-nanometre control [S6].
Selection is a trade-off: PERC line conversions tend to pick PECVD for capex reuse and single-side processing, while greenfield capacity leans to LPCVD for efficiency headroom [S6]. Inline doping vs ex-situ doping further complicates the flow: in-situ doping (PH3 or POCl3 mixed into the poly-Si deposition) cuts a separate diffusion step, while ex-situ doping adds one furnace pass but gives more uniform sheet resistance (typically 80–150 Ω/□ on the rear poly-Si) [S6].
The front-side single-side etch (HF/HNO3) used to strip the parasitic BBr3 emitter before the rear TOPCon stack is widely cited as the most yield-sensitive wet step, because residual emitter on the rear destroys the passivation gain; well-controlled lines keep this etch uniformity to <2% across a 210 mm wafer batch [S5][S6].
Module integration: 1/3-cut, half-cut, bifacial, glass-glass
TOPCon cells are typically cut in half or 1/3 cells to reduce resistive losses and improve partial-shading tolerance, then laminated as glass-glass bifacial modules to capture rear-side gain [S3]. Catalogued 2025 module builds include 420–445 W full-black glass-glass (182 mm wafers, 108 half-cells, 21.5%–22.8% efficiency) and 570–595 W bifacial silver-frame glass-glass (210 mm wafers, 132 half-cells, 23.0%–23.87% efficiency) [S3].
Mechanical dimensions track the wafer: 1722×1134×30 mm for the 182 mm half-cell format and 1960×1134×30 mm for 210 mm formats, with palletisation of 864–936 modules per 40 HQ container [S3]. The glass-glass construction also qualifies TOPCon modules for 30-year power warranties in many vendor programmes versus 25 years for glass-backsheet builds, an important TCO lever for utility-scale buyers.
For process engineers, the practical takeaway on process choice: the field evidence in [S1] aligns with the metallization-and-passivation advantage that the TOPCon rear stack was designed to deliver, and the retrofittable process footprint documented in [S2][S6] explains why capacity has scaled into the 100 GW+ range cited in the same field report [S1].
Failure modes, limits and sourcing signals to track
The three top field-failure modes to watch on TOPCon lines are (1) rear poly-Si thickness drift causing Voc and fill-factor loss, (2) wrap-around emitter residue after the single-side etch that increases rear recombination current J0, and (3) metallization contact-resistance spikes when silver-paste firing profiles are pushed too cold to protect the tunnel oxide [S2][S5][S6].
Process-side sourcing signals worth tracking over the next two quarters include: LPCVD tube-furnace delivery lead times (a bottleneck through 2024–2025), PECVD in-line tool throughput in wafers/hour, and silver-paste price per kg as 18-busbar layouts push silver consumption per cell above 80 mg [S2][S3][S4]. Standards-wise, the relevant reference points are IEC 61215 and IEC 61730 for module qualification; reliability claims in vendor datasheets (e.g. the 25-year/30-year warranty terms above) should always be read against these [S3].
For a deeper look at the cost-of-electricity lever and how inverter pairing drives BOS economics on a 1 GW build, see Solar Inverter Smart Manufacturing: 2026 Power Bands, Cell Pairing and Audit Anchors.
For the manufacturing-equipment line-build picture behind the throughput claims above, see Lithium Cell Manufacturing Equipment: Process Stations, Spec Bands and Sourcing Map and the inline-AI/MES pattern in Separator Smart Manufacturing: Inline Vision, AI Inspection, MES Stack.
For component-level specifications, see additive manufacturing material, load cell, and load cell module.