Global DRAM wafer capacity is tracking toward roughly 1.67 million 300mm wafers per month by year-end 2026, after the industry added approximately 120,000 wafers per month during the year on a 1.55 million base, a +7.7% expansion in the standard supply model [S2].
The 2026 capacity cycle is structurally split: Samsung's Pyeongtaek P4 contributed about 80,000 wafers per month of that increment, SK hynix's M15X line layered on roughly 50,000 wafers per month of new output, and the remaining net adds came from Micron's HBM-dedicated conversion, with HBM now absorbing a disproportionate share of the industry's cleanroom space [S2][S3][S8].
SK hynix 1c Node: From 20K to 160-190K Wafers per Month
SK hynix is scaling its sixth-generation 10nm-class 1c DRAM from approximately 20,000 wafers per month at the start of 2026 to a target range of 160,000 to 190,000 wafers per month by year-end, an 8x to 9.5x ramp on a single node in roughly 12 to 18 months [S1]. The Cheongju M15X fab anchors the build: it entered the first half of 2026 with about 10,000 wafers per month in pilot and is scheduled to reach 50,000 wafers per month by Q4 2026, lifting total SK hynix DRAM input to roughly 600,000 to 620,000 wafers per month in the second half of the year [S3].
For procurement teams, the critical variable is not the headline ramp but yield maturation: 1c is SK hynix's most advanced DRAM process, and historical 10nm-class node yield curves require two to four quarters of volume production before stabilizing [S1]. A ramp of 140,000 to 170,000 wafers per month on a single leading-edge node compresses that timeline, which translates into qualification and lot-to-lot consistency risk for early 1c deliveries through 2026.
Samsung P4: 1c Conversion Targeting 200K+ Wafers per Month
Samsung is targeting more than 200,000 wafers per month of 1c DRAM capacity at Pyeongtaek P4 by the end of 2026, achieved primarily through line conversion from prior DRAM nodes and additional equipment rather than greenfield construction [S4]. Of the approximately 120,000 wafers per month of net DRAM adds in 2026, Samsung's P4 supplied about 80,000, with the remainder split between SK hynix M15X ramp and incremental node conversions across the Korean footprint [S2].
The P4 1c build is split between high-bandwidth memory (HBM) feed and advanced commodity DRAM output, which is why Samsung's HBM production capacity is targeted to expand about 50% in 2026 even as the company continues to work through 2025-vintage HBM4 yield gaps [S1][S4]. For the broader wafer balance, the implication is that a large fraction of P4's 1c wafers is HBM-bound rather than conventional DDR5, a structural shift that tightens commodity DRAM availability even when total wafer counts rise.
Micron: 60K Wafers per Month HBM Expansion, 100K HBM Total
Micron announced on September 4, 2026 (via TrendForce) that it will add 60,000 HBM wafers per month, bringing its total HBM-specific capacity to approximately 100,000 wafers per month as HBM4 qualification progresses [S8]. This is incremental to, not separate from, the 1.55M-base industry total in the chipstrat supply model, and it directly reduces the share of Micron's wafer output feeding conventional DDR5 and LPDDR channels.
The 60,000 wafers per month figure is best read against the 1c scaling at SK hynix and Samsung: HBM stacks consume roughly 4x the wafer area of an equivalent-bit DDR5 product, so every 10,000 HBM wafers per month translates to a 30,000-40,000 wafer per month opportunity cost in conventional DRAM bit terms [S6]. The mix rebalancing is what makes 2026's headline wafer growth understate the actual tightening in commodity DRAM supply.
Mix, HBM Absorption, and What 6-8% Growth Actually Means in Bits
Total DRAM wafer starts are growing roughly 6-8% year over year exiting 2026, but the bit growth available to non-HBM customers is materially lower because HBM's 4x wafer-intensity multiplier absorbs a growing slice of the wafer base [S5][S6]. In SK hynix's case, HBM is already approximately 30% of DRAM capacity in 2026, with a projected rise to nearly 40% by 2027 [S3].
The practical engineering takeaway for buyers: headline wafer growth of 6-8% does not equal 6-8% more conventional DRAM bits available. Adjusted for HBM wafer pull-through, effective commodity DRAM wafer growth exiting 2026 is closer to 3-5%, which is one of the structural reasons the 2026 market cleared at sharply higher ASPs (conventional DDR5 approaching $1.20-$1.30 per Gb in some contract prints) [S5]. For comparison, the 2017-18 cycle delivered a roughly 90% price rise; the 2025-27 trajectory is on track for a 275-300% cumulative price increase, more than three times that prior super cycle, on a base that itself tripled [S5].
Cleanroom Constraint, 2027 Relief, and the 150K Wafers per Month Bracket
The dominant physical bottleneck is not lithography tool lead times (though EUV-dependent tools run 12-18 months) but cleanroom square footage at the major Korean fabs [S1][S4]. SK Securities estimates that once new Korean fabs are completed in the first half of 2027, each of Samsung and SK hynix will have enough cleanroom space to support an additional 150,000 wafers per month of capacity [S4]. Until that footprint is online, cleanroom-constrained line conversion is the only practical supply lever, which caps the 2026 net-add at the observed 120,000 wafers per month even though demand-side orders would justify more.
The capacity-to-demand gap is the single most important signal to track through 2026, and the cleanroom-construction milestones at Pyeongtaek P5 and Cheongju M16 are the next observable data points.
For context on how this DRAM wafer expansion interacts with the advanced-packaging bottleneck upstream of HBM stacking, the CoWoS-L vs CoWoS-S 2026 allocation picture is the natural next read, since HBM4 wafer growth only converts to shippable product if TSMC's CoWoS line keeps pace.
Spec-level background on the components involved: pressure transmitter, flow meter, and industrial valve.